1. D. Das Sharma, “UCIe™ 3.0: Backwards Compatible Evolution -  Doubling Bandwidth, Addressing New Usage Models, and Enhanced Manageability for Seamless Interoperability”, Invited talk, International Test Conference, Sept 2025, San Diego, CA
  2. D. Das Sharma and Y. Zorian, “UCIe 3.0-based Multi-chiplets: Design and Test”, Tutorial, International Test Conference, Sept 2025, San Diego, CA
  3. D. Das Sharma, “Introducing the UCIeTM 3.0 Specification: Continued Innovations in the Open Chiplet Ecosystem”, webinar by UCIe consortium, Sept 18, 2025, https://www.youtube.com/watch?v=EvaY4NHlfWI 
  4. D. Das Sharma et. al., Moderator and Lead Panelist, “Composable Infrastructure for AI – The Convergence of Storage, Interconnect, and Compute”, AI Infrastructure Summit, Santa Clara, CA, Sept 2025
  5. D. Das Sharma et. al., “On-Package Memory with Universal Chiplet Interconnect Express (UCIe): A Low Power, High Bandwidth, Low Latency, and Low Cost Approach”, IEEE Hot Interconnects, Aug 2025. https://www.youtube.com/watch?v=7DLrqVl_2m8. https://arxiv.org/abs/2510.06513 
  6. D. Das Sharma, “On-Package Chiplet Innovations with Universal Chiplet Interconnect ExpressTM (UCIeTM)”, keynote and panelist on `Chiplets and Advanced Packaing’ track at OCP Asia, Taipei, Aug 2025 
  7. D. Das Sharma, “Architecting the Future: Server Design in the Age of AI with PCI-Express® Technology”, Invited Talk and Panelist in Server Track at OCP Asia, Taipei, Aug 2025
  8. D. Das Sharma, “On-Package Open Chiplet Innovations with Universal Chiplet Interconnect Express (UCIe)”, Cubic/Chimes Joint Workshop”, June 24, 2025, Columbia University, NY
  9. D. Das Sharma, “PCIe® 7.0 PHY Logical”, PCI-SIG Developers Conference, June 2025, Santa Clara, CA
  10. D. Das Sharma, “Optical-friendly evolution of PCI-Express®”, PCI-SIG Developers Conference, June 2025, Santa Clara, CA
  11. D. Das Sharma, et. al., “PCI-SIG Technical Workgroup Panel”, PCI-SIG Developers Conference, June 2025, Santa Clara, CA
  12. D. Das Sharma, “UCIe 2.0TM: Open Chiplet Innovation continues with Vertical and Planar Connectivity”, 2025 IEEE EPS Build-Up Substrate Symposium, May 9, 2025, Milpitas, CA
  13. D. Das Sharma, “CXL is Future Focused”, 2025 CXL Developers Conference, April 30, 2025, Santa Clara, CA
  14. D. Das Sharma, B. Vaisband, J. Lee, S. Klinger, “Critical Enabling Technologies” Panel for the theme “Future of Computing: Sustainable AI Systems”, organized by M. Grupen-Shemansky, VP and CTO of SEMI, at SEMI, Milpitas, CA, Mar 19, 2025
  15. R. Ahlvers, P. Cayton, D. Das Sharma, J. Metz, K. Bowman, J. Autor, “Industry standards working together to accelerate innovation in AI and HPC”, Panel at ACM/IEEE Supercomputing SC24, Atlanta, Nov. 2024
  16. D. Das Sharma, “PCIe® 6.0 and 7.0 PHY Logical”, 2024 PCI-SIG India Developers’ Conference, Nov 11, Bangalore
  17. D. Das Sharma and Y. Zorian, “UCIe 2.0 based Multi-Chiplets Design and Test”, Tutorial, 2024 International Test Conference, San Diego, Nov 4
  18. D. Das Sharma, “UCIeTM 2.0: Momentum continues on open chiplet ecosystem”, IEEE Micro HipChips Workshop, Nov 2, 2024, Austin
  19. D. Das Sharma and S. Glaser, “Unordered IO for Improving Performance and Efficiency of PCIe® Fabrics for AI/ML Applications”, Oct 2024, Webinar by PCI-SIG, https://www.youtube.com/watch?v=-GJzE7zwX4c 
  20. D. Das Sharma, “Introducing the UCIe 2.0 Specification: Supporting 3D Packaging and Manageability System Architecture”, Webinar by UCIe Consortium, Sept 19, 2024 (https://www.youtube.com/watch?v=SgFQMqG8o_U) 
  21. D. Das Sharma, “UCIe 2.0 Specification: Advancing an open ecosystem for on-package chiplet innovation”, 2024 SNIA Storage Developers Conference, Santa Clara, Sept 18, 2024
  22. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Interconnect Standard for Innovations On-Package”, IEEE SSCS/EDS Chapter in Hawaii, Sept 11, 2024 
  23. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Interconnect Standard for Innovations On-Package”, IEEE Computer Society Israel, Aug 26, 2024
  24. D. Das Sharma, “UCIe 2.0 Specification: Advancing an open ecosystem for on-package chiplet innovation”, 2024 FMS (Future Memory and Storage) Summit, Santa Clara, Aug 8, 2024
  25. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Interconnect Standard for Innovations On-Package”, Special Seminar, Dept of CS, Stanford University, June 6, 2024 
  26. D. Das Sharma, “Compute Express Link (CXL)*: An open interconnect for HPC and AI applications”, International Supercomputing Conference Exacomm 2024 Workshop, May 2024
  27. D. Das Sharma, “CXL* Specifications Overview”, CXL Developers Conference, April 2024, Santa Clara, CA
  28. D. Das Sharma, “Compute Express Link (CXL*): Changing the Compute Landscape”, Dept of ECE, University of California, Santa Cruz, Apr 29, 2024
  29. D. Das Sharma, “Chiplets: On-Package Interconnects for Generative AI and Beyond”, Asilomar Microcomputer Workshop, April 2024
  30. D. Das Sharma, D. Harriman, M. Nilange, and R. Solomon, “Celebrating 20 years of the PCIe specification”, public webinar as a panel moderated by M. Erler, PCI-SIG, Apr 10, 2024.
  31. D. Das Sharma (Panel Moderator), P. Crumley, M. Wadekar, “How to improve data movement using accelerated networks?”, Memcon 2024, Mar 26, Computer History Museum, Mountain View, CA
  32. D. Das Sharma et. al., Panel 4, to present views on chiplets and the relevance of Digital Twin, NIST Digital Twin Technical Standards Workshop, organized by Giulia Pedrielli, Dec 15, 2023, Washington, DC
  33. D. Das Sharma, “Chiplet Ecosystem with UCIe”, 2023 Chips R&D Chiplets Workshop, Panel 4, NIST conference, Dec 13, 2023, Washington, DC
  34. D. Das Sharma, “PCIe 6.0® PHY Logical”, PCI-SIG Developers’ Conference, Nov 2023, Bangalore, India
  35. Panelist at the IEEE EPS and CEDA Joint Panel at International Microsystems, Packaging, Assemby, and Circuits Technology (iMPACT) 2023 Conference on “Co-Design for AI”, moderated by Dr. Yao-Wen Chang of NTU, at Taipei, October 23, 2023
  36. D. Das Sharma, “The UCIeTM 1.1 Specification: Future Applications of Chiplets”, public webinar by UCIe consortium, Oct 12, 2023
  37. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)TM: An Open Chiplet Standard for on-package Innovation”, invited panel talk at 2023 International Test Conference, Oct 10, 2023, Anaheim, CA
  38. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)TM : An open industry standard for Chiplets”, 2023 IEEE Electronic Design Process Symposium (EPDS), Sunnyvale, CA, Oct 2023
  39. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Standard for Constructing SoCs”, 2023 Autonomous Vehicle Computing Conference (AVCC), Cambridge, UK, Sept 2023
  40. D. Das Sharma, “Compute Express Link (CXL): An Open Interconnect Standard for building Composable Systems”, Japan Green Data Center Committee, Sept 2023
  41. D. Das Sharma, “Perspective from CXL and UCIe Standards Efforts”, invitational input to Industry Advisory Committee (IAC) for Chips Act, Sept 2023
  42. D. Das Sharma, “Compute Express LinkTM(CXLTM): Enabling an interoperable ecosystem for heterogeneous memory and computing solutions”, 2023 SNIA Storage Developers’ Conference, Fremont, CA
  43. D. Das Sharma, “PCIe® 7.0 Specification: 128 GT/s Bandwidth for Future Data-Intensive Markets”, 2023 SNIA Storage Developers’ Conference, Fremont, CA
  44. D. Das Sharma, “SoC Construction Using Universal Chiplet Interconnect ExpressTM (UCIeTM): A Game Changer”, 2023 SNIA Storage Developers’ Conference, Fremont, CA
  45. D. Das Sharma, N. Kalyanasundaram, et. al., “Chiplets/ UCIe”, organizer of the tutorial and and speaker on “UCIe Overview and Usage Models”, Hot Chips 2023. https://www.youtube.com/watch?v=6esyPiEe_xE 
  46. D. Das Sharma, “Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0”, IEEE Hot Interconnects, 2023
  47. D. Das Sharma, “UCIeTM: Building an open ecosystem for chiplets for on-package innovations”, invited talk at Flash Memory Summit 2023, covered by Forbes. 
  48. D. Das Sharma, B. Fleischer, D. Sabur, J. O’Hare, and C. Park, “What is the difference between a memory chip and a memory chiplet”, Panel organized by C. Sobey at Flash Memory Summit 2023
  49. D. Das Sharma, M. Wagh, M. Natu, and V. Hache, “Introduction to CXL”, Tutorial at Flash Memory Summit 2023, organized by D. Das Sharma
  50. D. Das Sharma, N. Kalyanasundaram, Z. Wu, and  S. Choudhary, “Introduction to UCIe”, Tutorial at Flash Memory Summit 2023, organized by D. Das Sharma
  51. D. Das Sharma, “Compute Express Link (CXL): An Open Interconnect for Cloud Infrastructure”, Invited paper and talk at DAC 2023, San Francisco
  52. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)TM : An open industry standard approach driving innovations at package level”, Invited talk at DAC 2023, San Francisco
  53. D. Das Sharma, “PCIe 6.0® PHY Logical”, PCI-SIG Developers’ Conference, June 2023, Santa Clara, CA
  54. D. Das Sharma et al, “PCIe Strategic Vision”, panel discussion with PCI-SIG Board, PCI-SIG Developers’ Conference, June 2023, Santa Clara, CA
  55. D. Das Sharma, C. Park, D. Ernst, and B. Falasfi, “Innovation with Load-Store Interconnects (PCIe, CXL, UCIe) in Supercomputing Landscape”, led this invited Focus Session, International Super Computing Conference, May 2023, Hamburg
  56. D. Das Sharma, “Compute Express Link (CXL)*: Open Interconnect for Building Composable Systems”, Exacomm Workshop, May 2023, Hamburg
  57. D. Das Sharma, “Universal Chiplet Interconnect ExpressTM (UCIe™): Building an open ecosystem of chiplets for on-package innovations”, Rheinland-Pfalzische Technische Universitat (RPTU), Kaisealautern, Germany, May 2023
  58. D. Das Sharma et al, “Compute, Memory, and Storage Technology Trends for the Application Developer”, Panel arranged by SNIA and moderated by Tom Coughlin, Memcon 2023, Mountain View, March 2023
  59. D. Das Sharma, “Universal Chiplet Interconnect ExpressTM (UCIeTM): An Open Standard for Chiplet Innovations On-Package”, IEEE EPS 2023 Test TC, Mar 2023
  60. D. Das Sharma, “Universal Chiplet Interconnect ExpressTM (UCIeTM): An open standard for innovations at package level”, invited talk at the 2nd International Workshop on High Performance Chiplet and Interconnect Architectures (HiPChips), 2023, co-located with HPCA 2023, Feb 2023
  61. D. Das Sharma, “Compute Expess Link (CXL)R: A game-changer in the Data Center” invited talk and the subsequent panel at the Workshop on Heterogeneous and Composable memory, co-located with HPCA 2023, Feb 2023
  62. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)TM: An Open Industry-Standard Chiplet Interconnect for Next-Generation Systems on a Package”, invited talk, at ‘The  Future of Heterogeneous Multi-Core Architectures for AI and Other Specialized Processing’ Forum at San Francisco, ISSCC 2023
  63. D. Das Sharma, “Introduction to UCIe”, Feb 2023, public webinar by UCIe Consortium
  64. D. Das Sharma, D. Gonzales, M. Mazumder, “PCI Express Specification: A High-Bandwidth, Low-Latency Interface for the Compute Continuum”, Panel Session, Designcon 2023, Santa Clara
  65. D. Das Sharma et. al., “Compute Express Link™ (CXL™) 3.0: Enabling new usage models in composable disaggregated infrastructure”, Panel Session, Designcon 2023, Santa Clara
  66. T. Coughlin, D. Das Sharma, D. McIntyre, “New Directions in Memory Technology”, panel session organized by IEEE Spectrum, Designcon 2023, Santa Clara 
  67. D. Das Sharma, “Compute Express Link (CXL): Open Interconnect for building Composable Systems”, RESDIS workshop, Supercomputing 22, Dallas, Nov 2022
  68. D. Das Sharma and R. Solomon, “PCI-Express”, Panel session, Supercomputing 22, Dallas, Nov 2022
  69. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)TM: An Open Chiplet Standard for on-package Innovation”, invited talk, International Test Conference (ITC), Oct 2022
  70. D. Das Sharma, “CXL 3.0: Enabling composable systems with expanded fabric capabilities”, public webinar from CXL consortium, Oct 2022
  71. D. Das Sharma, “UCIeTM (Universal Chiplet Interconnect Express): Accelerating the future of semiconductor innovations in an open source environment”, Storage Developer Conference, SDC 22, Fremont, CA, Sept 2022
  72. D. Das Sharma, “PCIe® 6.0 Specification and beyond: Enabling Storage and Machine Learning Applications”, Storage Developer Conference, SDC 22, Fremont, CA, Sept 2022
  73. D. Das Sharma, “Compute Express Link®: An open industry-standard interconnect enabling heterogeneous data-centric computing” IEEE Hot Interconnects, Aug 2022
  74. D. Das Sharma, “PCI Express® Technology: What’s in the 6.0 Specification for Storage?”, Special 1-hour invited talk, Flash Memory Summit, Santa Clara, CA, Aug 2, 2022
  75. D. Das Sharma, “UCIe ™ (Universal Chiplet Interconnect Express™): An Open Industry Standard for Chiplets”, Special 1-hour invited talk, Flash Memory Summit, Santa Clara, CA, Aug 2, 2022
  76. D. Das Sharma, “CXL 3.0: New Features for Increased Scale & Optimized Resource Utilization”, Flash Memory Summit, Santa Clara, CA, Aug 3, 2022
  77. D. Das Sharma, “The History of PCI IO Technology: 30 Years of PCI-SIG® Innovation”, public webinar on behalf of PCI-SIG, June 29, 2022
  78. D. Das Sharma, “PCIe 6.0® PHY Logical”, PCI-SIG Developers’ Conference, June 2022, Santa Clara, CA
  79. D. Das Sharma et al, “PCIe panel discussion”, PCI-SIG Developers’ Conference, June 2022, Santa Clara, CA
  80. D. Das Sharm et. al., “Road to Chiplets”, Microelectronics Packaging and Test Engineering Council (MEPTEC) Panel, May 12, 2022 
  81. D. Das Sharma, et. al., “Compute Express Link (CXL)TM: Interconnect Innovation to optimize Next Generation Cloud and Enterprise Data Centers”, Panel Session, Intel Vision, May 2022, Dallas
  82. D. Das Sharma, “PCIe 6.0® Specification: A High-performance i/o interconnect for advanced networking applications”, Open Fabrics Alliance Conference, OFA 2022
  83. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Chiplet Standard for Innovation”, Invited Talk, Asilomar Microcomputer Workshop, Pacific Grove, CA, April 2022
  84. Panel conducted by Tom Coughlin, D. Das Sharma with 9 other panelists, “Digital Storage and Memory”, IEEE Computer, Jan 2022
  85. D. Das Sharma, “Compute Express Link (CXL*): Changing the industry landscape”, REDIS Workshop, HPC Asia, Jan 2022
  86. D. Das Sharma and G. Talbot, “PCI Express Specifications: Enabling Emerging Applications of Today and Tomorrow”, Panel Session, Design Automation Conference, San Francisco, Dec 2021
  87. D. Das Sharma and R. Solomon, “Ask the Experts: An Interactive Discussion about the PCI Express® 6.0 Specification”, Supercomputing 21, BoF session, Nov 18, 2021
  88. D. Das Sharma, “Compute Express Link: An Open Innovation Slot”, Taiwan Data Centric Symposium, Nov 2021
  89. D. Das Sharma and C. Peterson, “Compute Express Link: Driving Innovations in Compute Platforms”, Intel Innovate, Oct 2021
  90. D. Das Sharma, “A low latency approach to delivering alternate protocols with coherency and memory semantics using PCI Express® 6.0 PHY at 64.0 GT/s”, IEEE Hot Interconnects, Aug 19, 2021
  91. D. Das Sharma and A. Kumar, “Adoption of PCIe® Technology in IoT Applications”, public webinar by PCI-SIG, Aug 11, 2021, 177 live attendees on bright talk with 5.0 out of 5.0 score
  92. D. Das Sharma, “Future of Workforce”, IEEE Roundtable Meeting panelist organized by Tom Coughlin, June 29, 2021
  93. D. Das Sharma, “PCIe 6.0 PHY Logical”, PCI-SIG Developers Conference, May 2021, virtual
  94. D. Das Sharma, et al, “PCIe Panel Discussion”, PCI-SIG Developers Conference, May 2021, virtual
  95. D. Das Sharma, D. Harriman, G. Ruggles, G. Talbot, “PCIe Technology in the Data Center”, Technical Networking session discussion, PCI-SIG Developers Conference, May 2021, virtual
  96. D. Das Sharma, “Compute Express Link (CXL): An Open Standard Innovation Interconnect”, Invited External speaker for opening session of Western Digital’s IDTC CXL Workshop, May 20, 2021
  97. Techquickie, “PCI Express 6.0 is a big deal”, https://www.youtube.com/watch?v=VcrkZigYXak, provided the background materials and walked Riley through the details, more than 300K views within a day of it going live on Jan 11, 2021 and 500K views to-date
  98. D. Das Sharma and A. Danesh, “Introducing the Compute Express Link (CXL) 2.0 specification”, public webinar sponsored by CXL consortium, https://www.youtube.com/watch?v=98ncoAyvPLk&trk=organization-update-content_share-embed-video_share-article_title, 2500+ views 
  99. D. Das Sharma, G. Ward, K. Bowman, and T. Symons, “CXL and Gen Z”, Panel discussion at Supercomputing 2020, Nov 2020, hosted by Tom Coughlin
  100. 100.D. Das Sharma, “PCI Express* Architecture and HPC: The Driver Towards the PCIe® 6.0 Specification and Support for Future HPC Systems”, OCP Tech Week, Oct 2020
  101. 101.D. Das Sharma, “Understanding Compute Express Link: A Cache-coherent interconnect”, Storage Developers Conference, Sept 2020
  102. 102.D. Das Sharma and M. Wagh, “Compute Express Link (CXL*) Update”, Intel Road Map Update Meeting, Sept 2020 
  103. 103.D. Das Sharma interview on PCIe 6.0 with co-editor Timothy Prickett Morgan of The Next Platform TV, Aug 6, 2020. Starts at minute 15 through minute 26: https://www.nextplatform.com/2020/08/06/next-platform-tv-for-august-6-2020/. Also see a writeup by M. Morgan in https://www.nextplatform.com/2020/08/06/the-tech-tricks-that-make-pci-express-6-0-and-beyond-possible/ 
  104. 104.D. Das Sharma, “PCI Express® 6.0 at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability, and cost-effective interconnect”, Hot Interconnects, Aug 2020
  105. 105.D. Das Sharma, “PCIe 6.0 Specification: The Interconnect for I/O needs of the future”, June 3, 2020, public webinar with 1230 live attendees and a 4.9/5.0 score https://www.youtube.com/watch?v=jhehXwnu0Ss&feature=youtu.be (repeated on Aug 4, 2020 due to demand for an APAC-friendly timeslot with about 500 attendees), 2500 views in youtube
  106. 106.D. Das Sharma, “PCIe 6.0 PHY Logical”, June 2020, PCI-SIG Developers’ Conference (virtual)
  107. 107.D. Das Sharma, D. Harriman, and J. Cowan, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2020 (virtual)
  108. 108.D. Das Sharma, “Compute Express Link for EagleStream Platform”, DCDC Training session for Intel Data Center Customers, June 2020
  109. 109.D. Das Sharma, “Compute Express Link 1.1: Overview”, CXL Consortium Training, May 2020
  110. 110.D. Das Sharma, “Compute Express Link 2.0: Overview”, CXL Consortium Training, May 2020
  111. 111.D. Das Sharma, “CXL Update”, Intel Roadmap Update Meeting, March 2020.
  112. 112.D. Das Sharma, G. Ward, and K. Bowman, “An Introduction to Compute Express LinkTM (CXL) Technology”, CXL ConsortiumTM Webinar, Dec 12, 2019. https://www.youtube.com/watch?v=RpAshNmpqLQ&t=335s (9100 views)
  113. 113.D. Das Sharma, “Compute Express Link® (CXL):  A Coherent Interface for  Ultra-High-Speed Transfers”, Intel Roadmap Update Meeting, Sept 2019 
  114. 114.D. Das Sharma, “The New Generation of Storage: From PCI Express® 4.0 to PCI Express 6.0”, Flash Memory Summit, Santa Clara, Aug 2019 
  115. 115.D. Das Sharma, “PCIe 5.0 PHY Logical”, PCI-SIG Developers Conference, June 2019
  116. 116.G. Caruk, J. Cowan, D. Das Sharma, D. Gonzalez, and M. Nilange, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2019
  117. 117.D. Das Sharma, “Compute Express Link: An Overview”, CXL Consortium training event, July 2019, Austin
  118. 118.D. Das Sharma, “Compute Express Link: An Overview”, CXL Consortium training event, May 2019, Mountain View
  119. 119.D. Das Sharma, “Compute Express Link: An Overview”, CXL Consortium training event, March 2019, Santa Clara
  120. 120.D. Das Sharma, “PCI Express: What’s Next for Storage”, SNIA Storage Developers’ Conference, Santa Clara, Sept 2018. Made it to a Forbes.com article “SNIA SDC Dishes up Storage Innovations” by Tom Coughlin, https://www.forbes.com/sites/tomcoughlin/2018/09/30/snia-sdc-dishes-up-storage-innovations/#5e450a885a86
  121. 121.D. Das Sharma, “PCIe 5.0 /IAL Low Latency Re-timer”,2018 Repeater User and Developer Conference
  122. 122.D. Das Sharma, “PCIe 5.0 PHY Logical”, PCI-SIG Developers Conference, June 2018
  123. 123.G. Caruk, J. Cowan, D. Das Sharma, D. Froelich, D. Gonzalez, and M. Nilange, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2018
  124. 124.D. Das Sharma, “PCI Express® Technology: The Ubiquitous I/O Interconnect, Now in its Fifth Generation”, SNIA Storage Developers’ Conference, Santa Clara, Sept 2017
  125. 125.D. Das Sharma, “PCI-Express at Gen 4 moving to Gen 5: Driving the future of Storage”, Flash Memory Summit, August 2017
  126. 126.D. Das Sharma, “PCIe 4.0 PHY Logical", PCI-SIG Developers Conference, June 2017 
  127. 127.G. Caruk, J. Cowan, D. Das Sharma, D. Froelich, D. Gonzalez, and D. Harriman, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2017 
  128. 128.D. Das Sharma, “PCI Express: Driving the Future of Storage”, 2016 Flash Memory Summit in Santa Clara, Aug 2016
  129. 129.D. Das Sharma, “Chat with the Experts” session on PCIe SSDs, 2016 Flash Memory Summit in Santa Clara, Aug 2016
  130. 130.D. Das Sharma, “PCIe 4.0 PHY Logical”, PCI-SIG Developers Conference, Santa Clara, June 2016
  131. 131.D. Das Sharma, D. Froelich, D. Harriman, M. Nilange, G. Caruk, H. Newmann, and J. Cowan, “PCIe 4.0 Panel Discussion”, PCI-SIG Developers Conference, June 2016, Santa Clara, CA
  132. 132.D. Das Sharma, “Evolution of PCI Express as the ubiquitous I/O Interconnect Technology”, Open Server Summit, April 2016, Santa Clara
  133. 133.D. Das Sharma, Experts Table in Open Server Summit, April 2016, Santa Clara to discuss PCIe as a storage interface and its use with NVMe 
  134. 134.D. Das Sharma, “Evolution of PCI Express as the ubiquitous I/O Interconnect Technology”, Open Fabrics Alliance Conference, April 2016 
  135. 135.D. Das Sharma, “PCIe 4.0 Encoding”, PCI-SIG Developers Conference Asia Pacific tour 2015 in Shanghai, Tokyo, and Taipei
  136. 136.D. Das Sharma, “PCIe 4.0 Protocol Update”, PCI-SIG Developers Conference Asia Pacific tour 2015 in Shanghai, Tokyo, and Taipei
  137. 137.D. Froelich, R. Neshati, and D. Das Sharma, “PCI Express* 4.0  Technology Updates For Server and Workstation Systems”, IDF 2015, San Francisco
  138. 138.M. Altmann, D. Das Sharma, S. Kottapalli, C. Mozak, G. Pasdast, C. Sundararaman, M. Wagh, and Z. Wu, DTTC Birds of a Feather Session, “Multi-Chip Package Interface: Current Status and Future Directions”, Aug, 2015, Portland, OR
  139. 139.D. Das Sharma, D. Froelich, G. Caruk, and J. Cowan, “PCIe 4.0 Panel Discussion”, PCI-SIG Developers Conference, June 2015, Santa Clara, CA
  140. 140.D. Das Sharma, “PCIe 4.0 PHY Logical”, PCI-SIG Developers Conference, June 2015, Santa Clara, CA
  141. 141.A. Pethe and D. Das Sharma, “PCIe Updates for SoC Applications”, IDF 2014, San Francisco.
  142. 142.D. Das Sharma, “PCIe 3.x/4.0 Encoding and PHY Logical”, PCI-SIG Developers Conference, June 2014, Santa Clara, CA
  143. 143.D. Das Sharma, “PCIe 3.0 PHY Logical”, PCI-SIG Developers Conference, June 2013, Santa Clara, CA
  144. 144.D. Das Sharma, “PCIe 3.0 Encoding and Protocol Overview”, PCI-SIG Developers Conference, June 2011, Santa Clara, CA. 
  145. 145.D. Das Sharma, Chaired a DTTC Birds-Of-a-Feather Session on “IIO integration Challenges in CPU”, Portland, June 2011
  146. 146.D. Das Sharma, “PCIe 3.0 Encoding and Protocol Overview”, PCI-SIG Developers Conference Israel, March 2011
  147. 147.D. Das Sharma, “PCI Express* 3.0 Features and Requirements Gathering for beyond”, Invited Talk, Open Fabrics Alliance, April 2011, Monterey, CA.
  148. 148.D. Das Sharma, “PCI Express* 3.0 Technology: Logical PHY considerations for Intel® Platforms”, Intel Developer Forum, San Francisco, Fall 2010
  149. 149.D. Das Sharma, “PCIe 3.0 Encoding and PHY Logical”, PCI-SIG Developers Conference, June 2010, Santa Clara, CA
  150. 150.D. Das Sharma, Panelist in a DTTC Birds-Of-a-Feather Session on “Improving IO cost, time to market and innovation for leadership platforms”, Portland, June 2010
  151. 151.D. Das Sharma, “PCI Express* 3.0 Technology: Device Architecture Optimizations on Intel® Platforms”, Intel Developer Forum, Spring 2010, Beijing
  152. 152.D. Das Sharma, “PCI Express* 3.0 Technology: PHY Implementation Considerations on Intel® Platforms”, Intel Developer Forum, Spring 2010, Beijing
  153. 153.D. Das Sharma, “PCI Express* 3.0 Technology: Electrical Requirements for Designing ASICs on Intel® Platforms”, Intel Developer Forum, Spring 2010, Beijing
  154. 154.D. Das Sharma, “PCIe 3.0 Encoding and PHY Logical”, PCI-SIG PCIe Technology Seminar, Feb 2010, Milpitas, CA
  155. 155.D. Das Sharma, “PCIe 3.0 PHY Logical Layer”, PCI-SIG APAC Developers Conference, Oct 2009, Tokyo and Taipei.
  156. 156.D. Das Sharma, “Implementation Considerations for PCIe*3.0 PHY on Intel Platforms”, Intel Developer Forum, San Francisco, Fall 2009 (Rating Score: 8.77)
  157. 157.D. Das Sharma, “Intel® 5520 Chipset: An I/O Hub Chipset for Server, Workstation, and High End Desktop”, Hot Chips 2009.
  158. 158.D. Das Sharma, “PCIe 3.0 PHY Logical Layer Update”, PCI-SIG PCIe Technology Seminar, Dec 2008, Milpitas, CA
  159. 159.D. Das Sharma, “PCIe 3.0 PHY Logical Layer Update”, PCI-SIG PCIe Technology Seminar, Sept 2008, Milpitas, CA
  160. 160.D. Das Sharma, “PCI Express3.0* PHY Encoding Challenges and Considerations”, Intel Developer Forum, San Francisco, Fall 2008. (Evaluation score designation: Excellent)
  161. 161.D. Das Sharma, “PCIe 3.0 New Encoding Scheme (PCIe 3.0 Electricals III)”, PCI-SIG PCIe Developers’ Conference, June 2008, Santa Clara, CA. (Rated at 4.31 for effectiveness and 4.22 on quality on a scale of 1-5; 5 being the highest)
  162. 162.D. Das Sharma, “PCIe 3.0 PHY Logical Layer Requirements”, PCI-SIG PCIe Technology Seminar, April 2008, Taipei
  163. 163.D. Das Sharma, “PCIe 2.0 PHY Logical Sub-block”, PCI-SIG Developers Conference, PCI-SIG, May 2007, San Jose, CA
  164. 164.D. Das Sharma, “PCIe 2.0 Logical PHY Architecture”, PCI-SIG PCIe Technology Seminar, Dec 2006, Milpitas, CA.
  165. 165.D. Das Sharma, “PCIe 2.0 PHY Logical”, PCI-SIG APAC PCIe Technology Seminar, Oct 2006, Taipei.
  166. 166.D. Das Sharma, “Designing a 5GT/s PHY: Implementing the Logical State Machine”, Session Talk, Fall IDF, 2006, San Francisco. (Contribution recognized as Excellent)
  167. 167.D. Das Sharma, “PCIe 2.0 PHY Architecture”, PCI-SIG Developers Conference,  2006 in San Jose, California.
  168. 168.D. Das Sharma et. al., Panel session, “Ask the Experts” in PCI-SIG Developers Conference,  2006, in San Jose, California
  169. 169.D. Das Sharma, “Architectural Extensions and Optimizations in the PCI Express* PHY Layer”, Session Talk, Spring IDF, 2006, San Francisco. (Evaluation: Excellent)
  170. 170.D. Das Sharma, “PCIe 2.0 Architectural Extensions”, PCI-SIG Developers Conference Europe, 2006.
  171. 171.D. Froelich and D. Das Sharma, “PCIe* 2.0: 5 GHz Signaling and Logical Extensions Tutorial”, Forum Talk, Fall IDF 2005, Shanghai.
  172. 172.D. Das Sharma, “PCIe 2.0 Logical Extensions”, PCI-SIG PCIe Technology Seminar, Oct 3, 2005, Taipei.
  173. 173.D. Das Sharma, “PCIe* 2.0: 5GHz Logical Extensions”, Forum Talk, Fall IDF 2005, San Francisco
  174. 174.D. Das Sharma, D. Harriman, and B. Hosler, “PCI-Express™ Architecture and Enhancements”, Chalk Talk, Fall IDF 2005, San Francisco.
  175. 175.D. Das Sharma et al, “Industry Standards”, as an expert on PCIe, Think Tank, Fall IDF 2005, San Francisco.
  176. 176.D. Das Sharma and D. Harriman, “PCI Express Advanced Protocol Topics”, 2005 PCI-SIG Developers’ Conference, San Jose.
  177. 177.D. Das Sharma et. al., “TwinCastle: A Multi-processor North Bridge Server Chipset”, Hot Chips 2005.