Webinars/ Panels/ Invited Talks

1. Das Sharma et. al., Panel 4, to present views on chiplets and the relevance of Digital Twin, NIST Digital Twin Technical Standards Workshop, organized by Giulia Pedrielli, Dec 15, 2023, Washington, DC
2. Das Sharma, “Chiplet Ecosystem with UCIe”, 2023 Chips R&D Chiplets Workshop, Panel 4, NIST conference, Dec 13, 2023, Washington, DC
3. Das Sharma, “PCIe 6.0^® PHY Logical”, PCI-SIG Developers’ Conference, Nov 2023, Bangalore, India
4. Panelist at the IEEE EPS and CEDA Joint Panel at International Microsystems, Packaging, Assemby, and Circuits Technology (iMPACT) 2023 Conference on “Co-Design for AI”, moderated by Dr. Yao-Wen Chang of NTU, at Taipei, October 23, 2023
5. Das Sharma, “The UCIe^TM 1.1 Specification: Future Applications of Chiplets”, public webinar by UCIe consortium, Oct 12, 2023
6. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)^TM: An Open Chiplet Standard for on-package Innovation”, invited panel talk at 2023 International Test Conference, Oct 10, 2023, Anaheim, CA
7. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)^TM : An open industry standard for Chiplets”, 2023 IEEE Electronic Design Process Symposium (EPDS), Sunnyvale, CA, Oct 2023
8. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Standard for Constructing SoCs”, 2023 Autonomous Vehicle Computing Conference (AVCC), Cambridge, UK, Sept 2023
9. Das Sharma, “Compute Express Link (CXL): An Open Interconnect Standard for building Composable Systems”, Japan Green Data Center Committee, Sept 2023
10. Das Sharma, “Perspective from CXL and UCIe Standards Efforts”, invitational input to Industry Advisory Committee (IAC) for Chips Act, Sept 2023
11. Das Sharma, “Compute Express Link^TM(CXL^TM): Enabling an interoperable ecosystem for heterogeneous memory and computing solutions”, 2023 SNIA Storage Developers’ Conference, Fremont, CA
12. Das Sharma, “PCIe^® 7.0 Specification: 128 GT/s Bandwidth for Future Data-Intensive Markets”, 2023 SNIA Storage Developers’ Conference, Fremont, CA
13. Das Sharma, “SoC Construction Using Universal Chiplet Interconnect Express^TM (UCIe^TM): A Game Changer”, 2023 SNIA Storage Developers’ Conference, Fremont, CA
14. Das Sharma, N. Kalyanasundaram, et. al., “Chiplets/ UCIe”, organizer of the tutorial and and speaker on “UCIe Overview and Usage Models”, Hot Chips 2023
15. Das Sharma, “Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0”, IEEE Hot Interconnects, 2023
16. Das Sharma, “UCIe^TM: Building an open ecosystem for chiplets for on-package innovations”, invited talk at Flash Memory Summit 2023, covered by Forbes.
17. Das Sharma, B. Fleischer, D. Sabur, J. O’Hare, and C. Park, “What is the difference between a memory chip and a memory chiplet”, Panel organized by C. Sobey at Flash Memory Summit 2023
18. Das Sharma, M. Wagh, M. Natu, and V. Hache, “Introduction to CXL”, Tutorial at Flash Memory Summit 2023, organized by D. Das Sharma
19. Das Sharma, N. Kalyanasundaram, Z. Wu, and S. Choudhary, “Introduction to UCIe”, Tutorial at Flash Memory Summit 2023, organized by D. Das Sharma
20. Das Sharma, “Compute Express Link (CXL): An Open Interconnect for Cloud Infrastructure”, Invited paper and talk at DAC 2023, San Francisco
21. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)^TM : An open industry standard approach driving innovations at package level”, Invited talk at DAC 2023, San Francisco
22. Das Sharma, “PCIe 6.0^® PHY Logical”, PCI-SIG Developers’ Conference, June 2023, Santa Clara, CA
23. Das Sharma et al, “PCIe Strategic Vision”, panel discussion with PCI-SIG Board, PCI-SIG Developers’ Conference, June 2023, Santa Clara, CA
24. Das Sharma, C. Park, D. Ernst, and B. Falasfi, “Innovation with Load-Store Interconnects (PCIe, CXL, UCIe) in Supercomputing Landscape”, led this invited Focus Session, International Super Computing Conference, May 2023, Hamburg
25. Das Sharma, “Compute Express Link (CXL)*: Open Interconnect for Building Composable Systems”, Exacomm Workshop, May 2023, Hamburg
26. Das Sharma, “Universal Chiplet Interconnect Express^TM (UCIe™): Building an open ecosystem of chiplets for on-package innovations”, Rheinland-Pfalzische Technische Universitat (RPTU), Kaisealautern, Germany, May 2023
27. Das Sharma et al, “Compute, Memory, and Storage Technology Trends for the Application Developer”, Panel arranged by SNIA and moderated by Tom Coughlin, Memcon 2023, Mountain View, March 2023
28. Das Sharma, “Universal Chiplet Interconnect Express^TM (UCIe^TM): An Open Standard for Chiplet Innovations On-Package”, IEEE EPS 2023 Test TC, Mar 2023
29. Das Sharma, “Universal Chiplet Interconnect Express^TM (UCIe^TM): An open standard for innovations at package level”, invited talk at the 2^nd International Workshop on High Performance Chiplet and Interconnect Architectures (HiPChips), 2023, co-located with HPCA 2023, Feb 2023
30. Das Sharma, “Compute Expess Link (CXL)^R: A game-changer in the Data Center” invited talk and the subsequent panel at the Workshop on Heterogeneous and Composable memory, co-located with HPCA 2023, Feb 2023
31. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)^TM: An Open Industry-Standard Chiplet Interconnect for Next-Generation Systems on a Package”, invited talk, at ‘The Future of Heterogeneous Multi-Core Architectures for AI and Other Specialized Processing’ Forum at San Francisco, ISSCC 2023
32. Das Sharma, “Introduction to UCIe”, Feb 2023, public webinar by UCIe Consortium
33. Das Sharma, D. Gonzales, M. Mazumder, “PCI Express Specification: A High-Bandwidth, Low-Latency Interface for the Compute Continuum”, Panel Session, Designcon 2023, Santa Clara
34. Das Sharma et. al., “Compute Express Link™ (CXL™) 3.0: Enabling new usage models in composable disaggregated infrastructure”, Panel Session, Designcon 2023, Santa Clara
35. Coughlin, D. Das Sharma, D. McIntyre, “New Directions in Memory Technology”, panel session organized by IEEE Spectrum, Designcon 2023, Santa Clara
36. Das Sharma, “Compute Express Link (CXL): Open Interconnect for building Composable Systems”, RESDIS workshop, Supercomputing 22, Dallas, Nov 2022
37. Das Sharma and R. Solomon, “PCI-Express”, Panel session, Supercomputing 22, Dallas, Nov 2022
38. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)^TM: An Open Chiplet Standard for on-package Innovation”, invited talk, International Test Conference (ITC), Oct 2022
39. Das Sharma, “CXL 3.0: Enabling composable systems with expanded fabric capabilities”, public webinar from CXL consortium, Oct 2022
40. Das Sharma, “UCIe^TM (Universal Chiplet Interconnect Express): Accelerating the future of semiconductor innovations in an open source environment”, Storage Developer Conference, SDC 22, Fremont, CA, Sept 2022
41. Das Sharma, “PCIe® 6.0 Specification and beyond: Enabling Storage and Machine Learning Applications”, Storage Developer Conference, SDC 22, Fremont, CA, Sept 2022
42. Das Sharma, “Compute Express Link^®: An open industry-standard interconnect enabling heterogeneous data-centric computing” IEEE Hot Interconnects, Aug 2022
43. Das Sharma, “PCI Express^® Technology: What’s in the 6.0 Specification for Storage?”, Special 1-hour invited talk, Flash Memory Summit, Santa Clara, CA, Aug 2, 2022
44. Das Sharma, “UCIe ™ (Universal Chiplet Interconnect Express™): An Open Industry Standard for Chiplets”, Special 1-hour invited talk, Flash Memory Summit, Santa Clara, CA, Aug 2, 2022
45. Das Sharma, “CXL 3.0: New Features for Increased Scale & Optimized Resource Utilization”, Flash Memory Summit, Santa Clara, CA, Aug 3, 2022
46. Das Sharma, “The History of PCI IO Technology: 30 Years of PCI-SIG® Innovation”, public webinar on behalf of PCI-SIG, June 29, 2022
47. Das Sharma, “PCIe 6.0^® PHY Logical”, PCI-SIG Developers’ Conference, June 2022, Santa Clara, CA
48. Das Sharma et al, “PCIe panel discussion”, PCI-SIG Developers’ Conference, June 2022, Santa Clara, CA
49. Das Sharm et. al., “Road to Chiplets”, Microelectronics Packaging and Test Engineering Council (MEPTEC) Panel, May 12, 2022
50. Das Sharma, et. al., “Compute Express Link (CXL)^TM: Interconnect Innovation to optimize Next Generation Cloud and Enterprise Data Centers”, Panel Session, Intel Vision, May 2022, Dallas
51. Das Sharma, “PCIe 6.0^® Specification: A High-performance i/o interconnect for advanced networking applications”, Open Fabrics Alliance Conference, OFA 2022
52. Das Sharma, “Universal Chiplet Interconnect Express (UCIe): An Open Chiplet Standard for Innovation”, Invited Talk, Asilomar Microcomputer Workshop, Pacific Grove, CA, April 2022
53. Panel conducted by Tom Coughlin, D. Das Sharma with 9 other panelists, “Digital Storage and Memory”, IEEE Computer, Jan 2022
54. Das Sharma, “Compute Express Link (CXL*): Changing the industry landscape”, REDIS Workshop, HPC Asia, Jan 2022
55. Das Sharma and G. Talbot, “PCI Express Specifications: Enabling Emerging Applications of Today and Tomorrow”, Panel Session, Design Automation Conference, San Francisco, Dec 2021
56. Das Sharma and R. Solomon, “Ask the Experts: An Interactive Discussion about the PCI Express® 6.0 Specification”, Supercomputing 21, BoF session, Nov 18, 2021
57. Das Sharma, “Compute Express Link: An Open Innovation Slot”, Taiwan Data Centric Symposium, Nov 2021
58. Das Sharma and C. Peterson, “Compute Express Link: Driving Innovations in Compute Platforms”, Intel Innovate, Oct 2021
59. Das Sharma, “A low latency approach to delivering alternate protocols with coherency and memory semantics using PCI Express® 6.0 PHY at 64.0 GT/s”, IEEE Hot Interconnects, Aug 19, 2021
60. Das Sharma and A. Kumar, “Adoption of PCIe^® Technology in IoT Applications”, public webinar by PCI-SIG, Aug 11, 2021, 177 live attendees on bright talk with 5.0 out of 5.0 score
61. Das Sharma, “Future of Workforce”, IEEE Roundtable Meeting panelist organized by Tom Coughlin, June 29, 2021
62. Das Sharma, “PCIe 6.0 PHY Logical”, PCI-SIG Developers Conference, May 2021, virtual
63. Das Sharma, et al, “PCIe Panel Discussion”, PCI-SIG Developers Conference, May 2021, virtual
64. Das Sharma, D. Harriman, G. Ruggles, G. Talbot, “PCIe Technology in the Data Center”, Technical Networking session discussion, PCI-SIG Developers Conference, May 2021, virtual
65. Das Sharma, “Compute Express Link (CXL): An Open Standard Innovation Interconnect”, Invited External speaker for opening session of Western Digital’s IDTC CXL Workshop, May 20, 2021
66. Techquickie, “PCI Express 6.0 is a big deal”, https://www.youtube.com/watch?v=VcrkZigYXak, provided the background materials and walked Riley through the details, more than 300K views within a day of it going live on Jan 11, 2021 and 500K views to-date
67. Das Sharma and A. Danesh, “Introducing the Compute Express Link (CXL) 2.0 specification”, public webinar sponsored by CXL consortium, https://www.youtube.com/watch?v=98ncoAyvPLk&trk=organization-update-content_share-embed-video_share-article_title, 2500+ views
68. Das Sharma, G. Ward, K. Bowman, and T. Symons, “CXL and Gen Z”, Panel discussion at Supercomputing 2020, Nov 2020, hosted by Tom Coughlin
69. Das Sharma, “PCI Express* Architecture and HPC: The Driver Towards the PCIe^® 6.0 Specification and Support for Future HPC Systems”, OCP Tech Week, Oct 2020
70. Das Sharma, “Understanding Compute Express Link: A Cache-coherent interconnect”, Storage Developers Conference, Sept 2020
71. Das Sharma and M. Wagh, “Compute Express Link (CXL*) Update”, Intel Road Map Update Meeting, Sept 2020
72. Das Sharma interview on PCIe 6.0 with co-editor Timothy Prickett Morgan of The Next Platform TV, Aug 6, 2020. Starts at minute 15 through minute 26: https://www.nextplatform.com/2020/08/06/next-platform-tv-for-august-6-2020/. Also see a writeup by M. Morgan in https://www.nextplatform.com/2020/08/06/the-tech-tricks-that-make-pci-express-6-0-and-beyond-possible/
73. Das Sharma, “PCI Express® 6.0 at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability, and cost-effective interconnect”, Hot Interconnects, Aug 2020
74. Das Sharma, “PCIe 6.0 Specification: The Interconnect for I/O needs of the future”, June 3, 2020, public webinar with 1230 live attendees and a 4.9/5.0 score https://www.youtube.com/watch?v=jhehXwnu0Ss&feature=youtu.be (repeated on Aug 4, 2020 due to demand for an APAC-friendly timeslot with about 500 attendees), 2500 views in youtube
75. Das Sharma, “PCIe 6.0 PHY Logical”, June 2020, PCI-SIG Developers’ Conference (virtual)
76. Das Sharma, D. Harriman, and J. Cowan, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2020 (virtual)
77. Das Sharma, “Compute Express Link for EagleStream Platform”, DCDC Training session for Intel Data Center Customers, June 2020
78. Das Sharma, “Compute Express Link 1.1: Overview”, CXL Consortium Training, May 2020
79. Das Sharma, “Compute Express Link 2.0: Overview”, CXL Consortium Training, May 2020
80. Das Sharma, “CXL Update”, Intel Roadmap Update Meeting, March 2020.
81. Das Sharma, G. Ward, and K. Bowman, “An Introduction to Compute Express Link^TM (CXL) Technology”, CXL Consortium^TM Webinar, Dec 12, 2019. https://www.youtube.com/watch?v=RpAshNmpqLQ&t=335s (9100 views)
82. Das Sharma, “Compute Express Link^® (CXL): A Coherent Interface for  Ultra-High-Speed Transfers”, Intel Roadmap Update Meeting, Sept 2019
83. Das Sharma, “The New Generation of Storage: From PCI Express^® 4.0 to PCI Express 6.0”, Flash Memory Summit, Santa Clara, Aug 2019

• Das Sharma, “PCIe 5.0 PHY Logical”, PCI-SIG Developers Conference, June 2019

85. Caruk, J. Cowan, D. Das Sharma, D. Gonzalez, and M. Nilange, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2019
86. Das Sharma, “Compute Express Link: An Overview”, CXL Consortium training event, July 2019, Austin
87. Das Sharma, “Compute Express Link: An Overview”, CXL Consortium training event, May 2019, Mountain View
88. Das Sharma, “Compute Express Link: An Overview”, CXL Consortium training event, March 2019, Santa Clara
89. Das Sharma, “PCI Express: What’s Next for Storage”, SNIA Storage Developers’ Conference, Santa Clara, Sept 2018. Made it to a Forbes.com article “SNIA SDC Dishes up Storage Innovations” by Tom Coughlin, https://www.forbes.com/sites/tomcoughlin/2018/09/30/snia-sdc-dishes-up-storage-innovations/#5e450a885a86
90. Das Sharma, “PCIe 5.0 /IAL Low Latency Re-timer”,2018 Repeater User and Developer Conference

• Das Sharma, “PCIe 5.0 PHY Logical”, PCI-SIG Developers Conference, June 2018

92. Caruk, J. Cowan, D. Das Sharma, D. Froelich, D. Gonzalez, and M. Nilange, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2018
93. Das Sharma, “PCI Express® Technology: The Ubiquitous I/O Interconnect, Now in its Fifth Generation”, SNIA Storage Developers’ Conference, Santa Clara, Sept 2017

• Das Sharma, “PCI-Express at Gen 4 moving to Gen 5: Driving the future of Storage”, Flash Memory Summit, August 2017
• Das Sharma, “PCIe 4.0 PHY Logical", PCI-SIG Developers Conference, June 2017 

96. Caruk, J. Cowan, D. Das Sharma, D. Froelich, D. Gonzalez, and D. Harriman, “PCIe Panel Discussion”, PCI-SIG Developers Conference, June 2017 
97. Das Sharma, “PCI Express: Driving the Future of Storage”, 2016 Flash Memory Summit in Santa Clara, Aug 2016
98. Das Sharma, “Chat with the Experts” session on PCIe SSDs, 2016 Flash Memory Summit in Santa Clara, Aug 2016
99. Das Sharma, “PCIe 4.0 PHY Logical”, PCI-SIG Developers Conference, Santa Clara, June 2016
100. Das Sharma, D. Froelich, D. Harriman, M. Nilange, G. Caruk, H. Newmann, and J. Cowan, “PCIe 4.0 Panel Discussion”, PCI-SIG Developers Conference, June 2016, Santa Clara, CA
101. Das Sharma, “Evolution of PCI Express as the ubiquitous I/O Interconnect Technology”, Open Server Summit, April 2016, Santa Clara
102. Das Sharma, Experts Table in Open Server Summit, April 2016, Santa Clara to discuss PCIe as a storage interface and its use with NVMe
103. Das Sharma, “Evolution of PCI Express as the ubiquitous I/O Interconnect Technology”, Open Fabrics Alliance Conference, April 2016
104. Das Sharma, “PCIe 4.0 Encoding”, PCI-SIG Developers Conference Asia Pacific tour 2015 in Shanghai, Tokyo, and Taipei
105. Das Sharma, “PCIe 4.0 Protocol Update”, PCI-SIG Developers Conference Asia Pacific tour 2015 in Shanghai, Tokyo, and Taipei
106. Froelich, R. Neshati, and D. Das Sharma, “PCI Express* 4.0 Technology Updates For Server and Workstation Systems”, IDF 2015, San Francisco
107. Altmann, D. Das Sharma, S. Kottapalli, C. Mozak, G. Pasdast, C. Sundararaman, M. Wagh, and Z. Wu, DTTC Birds of a Feather Session, “Multi-Chip Package Interface: Current Status and Future Directions”, Aug, 2015, Portland, OR
108. Das Sharma, D. Froelich, G. Caruk, and J. Cowan, “PCIe 4.0 Panel Discussion”, PCI-SIG Developers Conference, June 2015, Santa Clara, CA
109. Das Sharma, “PCIe 4.0 PHY Logical”, PCI-SIG Developers Conference, June 2015, Santa Clara, CA
110. Pethe and D. Das Sharma, “PCIe Updates for SoC Applications”, IDF 2014, San Francisco.
111. Das Sharma, “PCIe 3.x/4.0 Encoding and PHY Logical”, PCI-SIG Developers Conference, June 2014, Santa Clara, CA
112. Das Sharma, “PCIe 3.0 PHY Logical”, PCI-SIG Developers Conference, June 2013, Santa Clara, CA
113. Das Sharma, “PCIe 3.0 Encoding and Protocol Overview”, PCI-SIG Developers Conference, June 2011, Santa Clara, CA.
114. Das Sharma, Chaired a DTTC Birds-Of-a-Feather Session on “IIO integration Challenges in CPU”, Portland, June 2011
115. Das Sharma, “PCIe 3.0 Encoding and Protocol Overview”, PCI-SIG Developers Conference Israel, March 2011
116. Das Sharma, “PCI Express* 3.0 Features and Requirements Gathering for beyond”, Invited Talk, Open Fabrics Alliance, April 2011, Monterey, CA.
117. Das Sharma, “PCI Express* 3.0 Technology: Logical PHY considerations for Intel® Platforms”, Intel Developer Forum, San Francisco, Fall 2010
118. Das Sharma, “PCIe 3.0 Encoding and PHY Logical”, PCI-SIG Developers Conference, June 2010, Santa Clara, CA
119. Das Sharma, Panelist in a DTTC Birds-Of-a-Feather Session on “Improving IO cost, time to market and innovation for leadership platforms”, Portland, June 2010
120. Das Sharma, “PCI Express* 3.0 Technology: Device Architecture Optimizations on Intel® Platforms”, Intel Developer Forum, Spring 2010, Beijing
121. Das Sharma, “PCI Express* 3.0 Technology: PHY Implementation Considerations on Intel® Platforms”, Intel Developer Forum, Spring 2010, Beijing
122. Das Sharma, “PCI Express* 3.0 Technology: Electrical Requirements for Designing ASICs on Intel® Platforms”, Intel Developer Forum, Spring 2010, Beijing
123. Das Sharma, “PCIe 3.0 Encoding and PHY Logical”, PCI-SIG PCIe Technology Seminar, Feb 2010, Milpitas, CA
124. Das Sharma, “PCIe 3.0 PHY Logical Layer”, PCI-SIG APAC Developers Conference, Oct 2009, Tokyo and Taipei.
125. Das Sharma, “Implementation Considerations for PCIe*3.0 PHY on Intel Platforms”, Intel Developer Forum, San Francisco, Fall 2009 (Rating Score: 8.77)
126. Das Sharma, “Intel® 5520 Chipset: An I/O Hub Chipset for Server, Workstation, and High End Desktop”, Hot Chips 2009.
127. Das Sharma, “PCIe 3.0 PHY Logical Layer Update”, PCI-SIG PCIe Technology Seminar, Dec 2008, Milpitas, CA
128. Das Sharma, “PCIe 3.0 PHY Logical Layer Update”, PCI-SIG PCIe Technology Seminar, Sept 2008, Milpitas, CA
129. Das Sharma, “PCI Express3.0* PHY Encoding Challenges and Considerations”, Intel Developer Forum, San Francisco, Fall 2008. (Evaluation score designation: Excellent)
130. Das Sharma, “PCIe 3.0 New Encoding Scheme (PCIe 3.0 Electricals III)”, PCI-SIG PCIe Developers’ Conference, June 2008, Santa Clara, CA. (Rated at 4.31 for effectiveness and 4.22 on quality on a scale of 1-5; 5 being the highest)
131. Das Sharma, “PCIe 3.0 PHY Logical Layer Requirements”, PCI-SIG PCIe Technology Seminar, April 2008, Taipei
132. Das Sharma, “PCIe 2.0 PHY Logical Sub-block”, PCI-SIG Developers Conference, PCI-SIG, May 2007, San Jose, CA
133. Das Sharma, “PCIe 2.0 Logical PHY Architecture”, PCI-SIG PCIe Technology Seminar, Dec 2006, Milpitas, CA.
134. Das Sharma, “PCIe 2.0 PHY Logical”, PCI-SIG APAC PCIe Technology Seminar, Oct 2006, Taipei.
135. Das Sharma, “Designing a 5GT/s PHY: Implementing the Logical State Machine”, Session Talk, Fall IDF, 2006, San Francisco. (Contribution recognized as Excellent)
136. Das Sharma, “PCIe 2.0 PHY Architecture”, PCI-SIG Developers Conference, 2006 in San Jose, California.
137. Das Sharma et. al., Panel session, “Ask the Experts” in PCI-SIG Developers Conference, 2006, in San Jose, California
138. Das Sharma, “Architectural Extensions and Optimizations in the PCI Express* PHY Layer”, Session Talk, Spring IDF, 2006, San Francisco. (Evaluation: Excellent)
139. Das Sharma, “PCIe 2.0 Architectural Extensions”, PCI-SIG Developers Conference Europe, 2006.
140. Froelich and D. Das Sharma, “PCIe* 2.0: 5 GHz Signaling and Logical Extensions Tutorial”, Forum Talk, Fall IDF 2005, Shanghai.
141. Das Sharma, “PCIe 2.0 Logical Extensions”, PCI-SIG PCIe Technology Seminar, Oct 3, 2005, Taipei.
142. Das Sharma, “PCIe* 2.0: 5GHz Logical Extensions”, Forum Talk, Fall IDF 2005, San Francisco
143. Das Sharma, D. Harriman, and B. Hosler, “PCI-Express™ Architecture and Enhancements”, Chalk Talk, Fall IDF 2005, San Francisco.
144. Das Sharma et al, “Industry Standards”, as an expert on PCIe, Think Tank, Fall IDF 2005, San Francisco.
145. Das Sharma and D. Harriman, “PCI Express Advanced Protocol Topics”, 2005 PCI-SIG Developers’ Conference, San Jose.
146. Das Sharma et. al., “TwinCastle: A Multi-processor North Bridge Server Chipset”, Hot Chips 2005.