DR. DEBENDRA DAS SHARMA

Patents Awarded by USPTO (205)

  1. D. Das Sharma, “Alternate Protocol Negotiation in a High Performance Interconnect”, US Patent No. 12,129,038, Issued Feb 4, 2025
  2. D. Das Sharma, “Source Ordering in Device Interconnects”, US Patent No. 12,216,607, Issued Feb 4, 2025
  3. R. Safranek, R. Blankenship, V. Iyer, J. Willey, R. Beers, D. Jue, A. Kumar, D. Das Sharma, et. al, “High Performance Interconnect”, US Patent No. 12,197,357, Issued Jan 14, 2025
  4. D. Das Sharma and S. Choudhary, “Forward Error Correction and Cyclic Redundancy Check Mechanisms for Latency-Critical Coherency and Memory Interconnects”, US Patent No. 12,189,470, Issued Jan 7, 2025 
  5. R. Safranek, R. Blankenship, V. Iyer, J. Willey, R. Beers, D. Jue, A. Kumar, D. Das Sharma, et. al, “High Performance Interconnect”, US Patent No. 12,189,550, Issued Jan 7, 2025
  6. D. Das Sharma, “Negotiating Asymmetric Link Widths dynamically in a Multi-Lane Link”, US Patent No. 12,164,457, Issued Dec 10, 2024
  7. D. Das Sharma, et. al., “Characterizing and Margining Multi-Voltage Signal Encoding for Interconnects”, US Patent No. 12,155,474, Issued Nov. 26, 2024
  8. D. Harriman, D. Das Sharma, D. Froelich, S. Stalley, “System, Method, and Apparatus for SRIS Mode Selection for PCIe”, US Patent No. 12,135,581, Issued Nov 5, 2024
  9. D. Das Sharma, “Pooled Memory Address Translation”, US Patent No.12,099,458, Issued Sept 24, 2024
  10. D. Das Sharma, “Flit-based Parallel-Forward Error Correction and Parity”, US Patent No. 11,934,261, Issued Mar 19, 2024
  11. D. Das Sharma, “Characterizing Error Correlation based on Error Logging for Computer Buses”, US Patent No. 11,886,312, Issued Jan 30, 2024
  12. D. Das Sharma, “SERDES Link Training”, US Patent No. 11,860,812, Issued Jan 2, 2024
  13. D. Das Sharma, “Precoding mechanism in PCI-Express”, US Patent No. 11,841,820, Issued Dec 12, 2023
  14. D. Das Sharma, “Partial Link Width States for Bidirectional Multilane Links”, US Patent No. 11,836,101, Issued Dec 5, 2023
  15. D. Das Sharma and S. Choudhary, “Shared Resources for Multiple Communication Traffics”, US Patent No. 11,818,058, Issued Nov. 14, 2023
  16. M. Jen, M. Gao, D.Das Sharma, F. Spagna, B. Tennant, and N. Dolev, “Recalibration of PHY circuitry for the PCI Express (PIPE) interface based on using a message bus interface, US Patent No. 11,789,892, Issued Oct 17, 2023
  17. D. Das Sharma and S. Choudhary, “Encoder and Decoder of Forward Error Correction (FEC)”, US Patent No. 11,770,138, Issued Sept 26, 2023
  18. S. Choudhary, D. Das Sharma, and R. Albion, “Streaming fabric interface (SFI) for computer buses”, US Patent No. 11,762,802, Issued Sept 19, 2023
  19. D. Das Sharma et al, “Shared buffer memory routing”, US Patent No. 11,755,486, Sept 12, 2023
  20. D. Das Sharma et al, “Shared buffer memory routing”, US Patent No. 11,755,486, Sept 12, 2023
  21. D. Das Sharma, “Alternate protocol negotiation in a high performance interconnect”, US Patent No. 11,758,028, Issued Sept 12, 2023
  22. D. Das Sharma, “Link Layer Communication by multiple Link Layer encodings for Computer Buses”, US Patent No. 11,743,109, Issued August 29, 2023
  23. R. Safranek, R. Blankenship, V. Iyer, J. Willey, R. Beers, D. Jue, A. Kumar, D. Das Sharma, et. al, “High Performance Interconnect”, US Patent No. 11,741,030, Issued August 29, 2023
  24. D. Das Sharma, “Multi-protocol support on common physical layer”, US Patent No. 11,740,958, Issued August 29, 2023
  25. D. Das Sharma et al, “Flex bus protocol negotiation and enabling sequence”, US Patent No. 11,726,939, Issued August 15, 2023
  26. D. Das Sharma et al, “Techniques to support multiple protocols between computer system interconnects”, US Patent No. 11,729,096, Issued August 15, 2023
  27. D. Froelich and D. Das Sharma, “Interconnect retimer enhancements”, US Patent No. 11,675,003, Issued June 13, 2023
  28. M. Jen, D. Das Sharma, B. Tennant, J. Prahladachar, “Enabling sync header suppression latency optimization in the presence of Retimers for serial interconnect”, US Patent No. 11,669,481, Issued June 6, 2023
  29. D. Das Sharma, A. Vasudevan, and D. Harriman, “Multiple Uplink Port Devices”, US Patent No. 11,657,015, Issued May 23, 2023 
  30. D. Das Sharma, “Low-latency Forward Error Correction for Serial Links”, US Patent No. 11,637,657, Issued Apr 25, 2023
  31. D. Harriman, D. Das Sharma, D. Froelich, and S. Stalley, “Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) mode selection for Peripheral Component Interconnect Express (PCIe)”, US Patent No. 11,630,480, Issued Apr 18, 2023
  32. Z. Wu, D. Das Sharma, M. Mazumder, S. Bastola, and K. Xiao, “PCI express enhancements”, US Patent No. 11,632,130, Issued Apr 18, 2023
  33. Z. Wu, D. Das Sharma, et. al., “High performance interconnect”, US Patent No. 11,599,497, Issued Mar 7, 2023
  34. D. Das Sharma, “Ordered sets for high-speed interconnects”, US Patent No. 11,595,318, Issued Feb 28, 2023
  35. D. Das Sharma, “SERDES Link Training”, US Patent No. 11,573,920, Issued Feb 7, 2023
  36. D. Das Sharma, “In-band retimer register access”, US Patent No. 11,561,910, Issued Jan 24, 2023
  37. D. Das Sharma, “Pooled memory address translation”, US Patent No. 11,507,528, Issued Nov 22, 2022
  38. D. Das Sharma, “Technologies for partial Link width states for multilane Links”, US Patent No. 11,474,960, Issued Oct 18, 2022
  39. D. Das Sharma, “Negotiating asymmetric Link widths dynamically in a multi-Lane Link”, US Patent No. 11,467,999, Issued Oct 11, 2022
  40. D. Das Sharma, “Link Layer Communication by multiple Link Layer encodings for Computer Buses”, US Patent No. 11,444,829, Issued Sept 13, 2022
  41. D.  Das Sharma, “Flit-based packetization”, US Patent No. 11,429,553, Issued Aug 30, 2022
  42. D. Das Sharma, “Retimer mechanisms for in-band Link management”, US Patent No. 11,397,701, Issued July 26, 2022
  43. D. Das Sharma et al, “Extending multichip package link off package”, US Patent No. 11,386,033, Issued July 12, 2022
  44. M. Jen, M. Gao, D. Das Sharma, F. Spagna, B. Tennant and N. Dolev, “PHY recalibration”, US Patent No. 11,327,920, Issued May 10, 2022
  45. D. Das Sharma and D. Froelich, “Cross-talk generation in a multi-Lane Link during Lane testing”, US Patent No. 11,327,861, Issued May 10, 2022
  46. D. Das Sharma, “Ordered sets for high-speed interconnects”, US Patent No. 11,296,994, Issued Apr 5, 2022
  47. D. Das Sharma and D. Froelich, “Adjustable Retimer Buffer”, US Patent No. 11,288,154, Issued Mar 29, 2022
  48. Z. Wu, D. Das Sharma, M. Mazumder, S. Bastola, and K. Xiao, “PCI express enhancements”, US Patent No. 11,283,466, Issued Mar 22, 2022
  49. R. Safranek, R. Blankenship, V. Iyer, J. Willey, R. Beers, D. Jue, A. Kumar, D. Das Sharma, et. al, “High Performance Interconnect”, US Patent No. 11,269,793, Issued March 8, 2022
  50. D. Das Sharma, “Flit-based parallel Forward-Error-Correction and Parity, US Patent No. 11,249,837”, Issued Feb 15, 2022
  51. A. Rao and D. Das Sharma, “Connecting accelerator resources using a switch”, US Patent No. 11,249,808, Issued Feb 15, 2022
  52. D. Das Sharma, “Width and frequency conversion with PHY layer devices, US Patent No. 11,239,843”, Issued Feb 1, 2022
  53. M. Jen, D. Das Sharma, B. Tennant, J. Prahladachar, “Enabling sync header suppression latency optimization in the presence of Retimers for serial interconnect”, US Patent No. 11,232,058, Issued Jan 25, 2022
  54. D. Das Sharma, “Forward error correction mechanism for data transmission across multi-Lane Links”, US Patent No. 11,223,446, Issued Jan 11, 2022
  55. D. Das Sharma, “Precoding mechanism in PCI-express”, US Patent No. 11,182,330, Issued Nov 23, 2021
  56. M. Jen, D. Froelich, D. Das Sharma, B. Tennant, Q. Devine, and S. W. Lim, “Reduced Pin Count Interface”, US Patent No. 11,163,717, Issued Nov 2, 2021
  57. D. Froelich, D. Das Sharma, F. Spagna, P. Fornberg, and D. Bradley, “In-band margin probing on an operational interconnect”, US Patent No. 11,157,350, Issued Oct 26, 2021
  58. D. Das Sharma, “Forward error correction mechanism for peripheral component interconnect-express (PCI-E)”, US Patent No. 11,153,032, Issued Oct 19, 2021
  59. D. Das Sharma et al, “Flex bus protocol negotiation and enabling sequence”, US Patent No. 11,144,492, Issued Oct 12, 2021 
  60. D. Das Sharma et al, “Extending multichip package link off-package”, US Patent No. 11,113,225,  Issued Sept 7, 2021
  61. D. Das Sharma et al, “Shared buffer memory routing”, US Patent No. 11,113,196, Issued Sept 7, 2021
  62. D. Das Sharma et al, “Techniques to support multiple protocols between computer system interconnects”, US Patent No. 11,095,556, Issued Aug 17, 2021
  63. D. Das Sharma and S. Choudhary, “Shared resources for multiple communication traffics”, US Patent No. 11,088,967, Issued Aug 10, 2021
  64. M. Schmisseur, M. J. Kumar, B. Fleischer, D. Das Sharma, R. Ramanujan, “Method and apparatus for dynamically allocating storage resources to compute nodes”, US Patent No 11,086,520, Issued Aug 10, 2021
  65. R. Safranek, R. Blankenship, and D. Das Sharma, “Multiple transaction data flow control unit for high-speed interconnect”, US Patent No. 11,061,850, Issued July 13, 2021
  66. Z. Wu, D. Das Sharma, M. Mazumder, S. Bastola, and K. Xiao, “PCI express enhancements”, USPTO No. 11,043,965, Issued June 22, 2021
  67. Z. Wu, M. Wagh, D. Das Sharma, et. al, “Multichip package link”, US Patent No. 11,003,610, Issued May 11, 2021
  68. D. Das Sharma, “Bypassing equalization at lower data rates”, USPTO No. 11,005,692, Issued May 11, 2021
  69. D.  Das Sharma, “Flit-based packetization for PCIe”, USPTO No. 10,997,111, Issued May 4, 2021
  70. D. Das Sharma, et al, “Sharing Memory and I/O services between nodes”, USPTO No. 10,915,468, Issued Feb 9, 2021
  71. D. Das Sharma, “Pooled memory address translation”, USPTO No. 10,877,916, Issued Dec 29, 2020
  72. D. Das Sharma, “Bypassing equalization at lower data rates”, USPTO No. 10,880,137, Issued Dec 29, 2020
  73. D. Das Sharma and D. Froelich, “Adjustable Retimer Buffer”, USPTO No. 10,860,449, Issued Dec 8, 2020
  74. Z. Wu, D. Das Sharma, A. A. Elsherbini, and G. Pasdast, “Inter-die passive interconnects approaching monolithic performance”, USPTO No. 10,854,548, Dec 1, 2020
  75. D. Das Sharma and D. Froelich, “Cross-talk generation in a multi-Lane Link during Lane testing”, USPTO No. 10,853,212, Issued Dec 1, 2020
  76. D. Das Sharma, “Partial Link width states for multilane Links”, USPTO No. 10,846,247, Issued Nov 24, 20202
  77. Zuoguo (Joe) Wu, Debendra Das Sharma, et al, “High Performance Interconnect”, USPTO No. 10,789,201, Issued Sept 29, 2020
  78. D. Das Sharma, “Forward Error Correction mechanism for Peripheral Component Interconnect-Express (PCI-e)”, USPTO No. 10,784,986, Issued Sept 22, 2020
  79. D. Das Sharma, “Forward error correction mechanism for data transmission across multi-Lane Links”, USPTO No. 10,771,189, Issued Sept 8, 2020
  80. M. Jen, D. Das Sharma, V. Iyer, and T. Liang, “Low Latency Retimer, USPTO No. 10,747,688”, Issued Aug 18, 2020
  81. M. Jen, M. Gao, D. Das Sharma, F. Spagna, B. Tennant and N. Dolev, “PHY recalibration”, USPTO No. 10,713,209, Issued July 14, 2020
  82. M. Jen, D. Froelich, D. Das Sharma, B. Tennant, Q. Devine, and S. W. Lim, “Reduced Pin Count Interface”, USPTO No. 10,706, 003, Issued July 7, 2020
  83. J. Bharadwaj, A. Brown, D. Das Sharma, and J. Thaliyil, “Live Error Recovery”, USPTO No. 10,691,520, Issued June 23, 2020
  84. D. Das Sharma, Z. Wu, M.Wagh, M. Mazumder, V. Iyer, and J. Morriss, “Extending multichip package link off package”, US Patent No. 10,678,736, Issued June 9, 2020
  85. D. Froelich, D. Das Sharma, F. Spagna, P. Fornberg, and D. Bradley, “In-band margin probing on an operational interconnect”, US Patent No. 10,671,476, Issued June 2, 2020
  86. D. Das Sharma, “Low latency multi-protocol retimers”, US Patent No. 10,606,793, Issued Mar 31, 2020
  87. D. Das Sharma, M. Jen, J. Prahladachar, B. Tennant, and M. Wagh, “Flex bus protocol negotiation and enabling sequence”, US Patent No. 10,606,785, Issued Mar 31, 2020
  88. D. Das Sharma, “Precoding mechanisms for devices coupled by a computer bus”, US Patent No. 10,606,790, Issued Mar 31, 2020
  89. D. Das Sharma, “Width and frequency conversion with PHY layer devices, US Patent No. 10,601,425”, Issued Mar 24, 2020
  90. Z. Wu, M. Wagh, D. Das Sharma, et. al, “Multichip package link”, US Patent No. 10,552,357, Issued Feb 4, 2020
  91. D. Froelich and D. Das Sharma, “Interconnect retimer enhancements”, US Patent No. 10,534,034, Issued Jan 14, 2020
  92. R. Safranek, R. Blankenship, and D. Das Sharma, “Multiple transaction data flow control unit for high-speed interconnect”, US Patent No. 10,503,688, Issued December 10, 2019
  93. D. Das Sharma, A. Vasudevan, and D. Harriman, “Multiple uplink port devices”, US Patent No 10,503,684, Issued Dec 10, 2019
  94. M. Schmisseur, M. J. Kumar, B. Fleischer, D. Das Sharma, R. Ramanujan, “Method and apparatus for dynamically allocating storage resources to compute nodes”, US Patent No 10,359,940, Issued July 23, 2019
  95. D. Das Sharma, M. J. Kumar, and B. Fleischer, “Data coherency model and protocol at cluster level”, US Patent No. 10,296,399, Issued May 21, 2019
  96. R. Safranek, R. Blankenship, V. Iyer, J. Willey, R. Beers, D. Jue, A. Kumar, D. Das Sharma, et. al, “High Performance Interconnect”, US Patent No. 10,248,591, Issued April 2, 2019
  97. D. Das Sharma, “Applying framing rules for a high speed data link”, US Patent No. 10,250,436, Issued April 2, 2019
  98. D. Das Sharma, M. J. Kumar, and B. Fleischer, “Assisted coherent shared memory”, US Patent 10,229,024, Issued March 12, 2019
  99. M. Jen, D. Froelich, D. Das Sharma, B. Tennant, Q. Devine, S. Lim, “Reduced Pin Count Interface”, US Patent No. 10,198,394, Issued on Feb 5, 2019
  100. D. Harriman, M. Kulkarni, A. Pethe, S. Stalley, M. Wagh, and D. Das Sharma, “Architecture for software defined interconnect switch”, US Patent No. 10,191,877, Issued on Jan 29, 2019
  101. D. Das Sharma, “Virtual Machine Migration in Rack Scale Systems”, US Patent No. 10,162,770, Issued on Dec 25, 2018
  102. V. Iyer, D. Jue, R. Blankenship, F. Spagna, D. Das Sharma, J. Swanson, “High performance interconnect physical layer”, US Patent No. 10,146,733, Issued Dec 4, 2018
  103. R. Safranek, R. Blankenship, and D. Das Sharma, “Multiple transaction data flow control unit for high-speed interconnect”, US Patent No. 10,078,617, Issued Sept 18, 2018
  104. Z. Wu, M. Wagh, D. Das Sharma, et. al, “Multichip package link”, US Patent No. 10,073,808, Issued Sept 11, 2018
  105. J. Bharadwaj, A. Brown, D. Das Sharma, and J. Thaliyil, “Live Error Recovery”, US Patent No. 10,019,300, Issued July 10, 2018
  106. D. Das Sharma, M. J. Kumar, and B. Fleischer, “Pooling of memory resources across multiple nodes”, US Patent No. 9,977,618, Issued May 22, 2018
  107. D. Das Sharma, “Low latency multi-protocol retimers”, US Patent No. 9,965,439, Issued May 8, 2018
  108. D. Das Sharma, “Pooled memory address translation”, US Patent No. 9,940,287, Issued Apr 10, 2018
  109. M. Jen, D. Das Sharma, M. Wagh, and V. Iyer, “Low power entry in a shared memory link”, US Patent No. 9,921,768, Issued Mar 20, 2018
  110. M. Schmisseur, M. J. Kumar, B. Fleischer, D. Das Sharma, R. Ramanujan, “Method and apparatus for dynamically allocating storage resources to compute nodes”, US Patent No 9,823,849, Issued Nov 21, 2017
  111. D. Das Sharma, D. Froelich, V. Iyer, M. Jen, R. Shah, E. Lee, “Physical interface for a serial interconnect”, US Patent No. 9,779,053, Issued October 3, 2017
  112. D. Das Sharma, M. Jen, and B. Morriss, “Shared buffered memory routing”, US Patent No. 9,720,838, Issued Aug 1, 2017
  113. V. Iyer, F. Spagna, and D. Das Sharma, “Redriver Link testing”, US Patent No. 9,692,589, Issued June 27, 2017
  114. D. Das Sharma, M. Jen, and J. Murray, “Low-latency internode communication”, US Patent No. 9,665,415, Issued May 30, 2017
  115. D. Das Sharma, S. Prasad, and J. Prahladachar, “Apparatus, system, and method for improving equalization with a hardware driven algorithm”, US Patent No. 9,645,965, Issued May 9, 2017
  116. R. Safranek, R. Blankenship, V. Iyer, J. Willey, R. Beers, D. Jue, A. Kumar, D. Das Sharma, et. al, “High Performance Interconnect”, US Patent No. 9.626,321, Issued April 18, 2017
  117. V. Iyer, R. Blankenship, and D. Das Sharma, “Probabilistic flit error checking”, US Patent No. 9,552,253, Issued January 24, 2017.
  118. D. Das Sharma and D. Froelich, “Test logic for a serial interconnect”, US Patent No. 9,552,269, Issued 24 Jan 2017. 
  119. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al., “Atomic operations in PCI express”, US Patent No. 9,535,838, Issued January 3, 2017.
  120. I. Pardo, I. Y. Soffair, D. Reif, D. Das Sharma, A. G. Pethe, Method and apparatus for high bandwidth dictionary compression technique using set update dictionary update policy, US Patent No. 9,514,085, Issued Dec 6, 2016 
  121. J. Prahladachar, D. Das Sharma, H. Poladia, and S. Prasad, “Method, apparatus, system for lane staggering and determinism for serial high speed I/O lanes”, US Patent No. 9,454,213, Issued Sept 27, 2016
  122. R. Safranek, R. Blankenship, and D. Das Sharma, “Multiple transaction data flow control unit for high-speed interconnect”, US Patent No. 9,442,879, Issued Sept 13, 2016.
  123. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al., “Transaction layer packet formatting”, US Patent No. 9,442,855, Issued Sept 13, 2016
  124. D. Das Sharma, M. J. Kumar, and B. Fleischer, “Data coherency model and protocol at cluster level”, US Patent No. 9,383,932, Issued July 5, 2016
  125. D. Das Sharma, M. J. Kumar, and B. Fleischer, “Assisted coherent shared memory”, US Patent No. 9,372,752, Issued June 21, 2016
  126. V. Iyer, D. Jue, R. Blankenship, F. Spagna, D. Das Sharma, J. Swanson, “High performance interconnect physical layer”, US Patent No. 9,355,058, Issued May 31, 2016
  127. D. Das Sharma, “Completion combining to improve effective link bandwidth by disposing at end of two-end link: A matching engine for outstanding non-posted transactions”, US Patent No. 9,317,466, Issued Apr 19, 2016
  128. I. Pardo, I. Y. Soffair, D.  Reif, D.  Das Sharma, A. G. Pethe, “Compression format for high bandwidth dictionary compression”, US Patent No. 9,306,598, Issued April 5, 2016
  129. J. Bharadwaj, A. Brown, D. Das Sharma, and J. Thaliyil, “Live Error Recovery”, US Patent No. 9,262,270, Issued Feb 16, 2016
  130. V. Iyer, D. Das Sharma, R. Blankenship, and D. Jue, “Embedded control channel for high speed serial interconnect”, US Patent No. 9,229,897, Issued Jan 5, 2016
  131. V. Iyer, D. Jue, R. Blankenship, F. Spagna, D. Das Sharma, and J. Swanson, “High-performance interconnect physical layer”, US Patent No. 9,208,121, Issued Dec 8, 2015
  132. V. Iyer, D. Das Sharma, R. Blankenship, and D. Jue, “Fast deskew when exiting low-power partial-width high speed link state”, US Patent No. 9,183,171, Issued Nov 10, 2015
  133. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al., “PCI Express Transaction Descriptor”, US Patent No. 9,089,415, Issued Aug 4, 2015
  134. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al., “Transaction re-ordering”, US Patent No. 9,032,103, Issued May 12, 2015
  135. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al., “Prefetching in PCI Express”, US Patent No. 9,026,682, Issued May 5, 2015
  136. D. Harriman, A. Foong, D. Das Sharma, “Apparatus, status and method for providing access to a device function”, US Patent No. 9,026,698, May 5, 2015
  137. D. Das Sharma, “Completion combining to improve effective link bandwidth by disposing at end of two-end link: A matching engine for outstanding non-posted transactions”, US Patent No. 8,935,453, Issued Jan 13, 2015
  138. I. Pardo, I. Soffair, D. Reif, D. Das Sharma, and A. Pethe, “Method and apparatus for high bandwidth dictionary compression technique using delayed dictionary update”, US Patent No. 8,909,880, Issued Dec 9, 2014
  139. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al., “Atomic Operations”, US Patent No. 8,793,404, Issued July 29, 2014
  140. S. Muthrasanallur, D. Das Sharma, S. Jayakrishna, and E. Wehage, “Method and System of Live Error Recovery”, US Patent No. 8,782,461, Issued Jul 15, 2014
  141. D. Das Sharma, C. P. Joshi, and G. Rajamani, “Increasing Input Output Hubs in constrained link based multiprocessor systems”, US Patent No. 8,782,318, Issued Jul 15, 2014
  142. R. Safranek, D. Das Sharma, G. Srinivasa, “Implementing quickpath interconnect protocol over a PCIe interface”,  US Patent No. 8,751,714, Issued Jun 10, 2014
  143. I. Pardo, I. Soffair, D. Reif, D. Das Sharma, and A. Pethe, “Compression format for high bandwidth dictionary compression”, US Patent No. 8665124, Issued Mar 4, 2014
  144. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 8,555,101, Issued Oct 8, 2013
  145. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 8,549,183, Issued Oct 1 2013
  146. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions including device window caching”, US Patent No: 8473642, Issued Jun 25, 2013
  147. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 8,447,888, Issued May 21, 2013
  148. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions including transactions having prefetch parameters”,  US Patent No. 8,230,119, Issued Jul 24, 2012
  149. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions including transactions”, US Patent No. 8230120, Issued Jul 24, 2012
  150. D. Das Sharma, G. Rajamani, and H. Hoang, “Strategy to verify asynchronous links across chips”, US Patent No. 8,209,563, Issued Jun 26, 2012
  151. A. Singhal, D. Das Sharma, J. Palomino, and M. A. Rubio, “Multiple compression techniques for packetized information”, US Patent No. 8,111,704, Issued Feb 7, 2012
  152. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions including transactions having prefetch parameters”,  US Patent No. 8,099,523, Issued Jan 17, 2012
  153. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 8,073,981, Issued Dec 6, 2011
  154. K. Drescher, D. Das Sharma, D. Sams, and R. Glass, “Enabling resynchronization of a logic analyzer”, US Patent No. 7,958,404, Issued Jun 7, 2011
  155. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 7,949,794, Issued May 24, 2011
  156. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 7,930,566, Issued Apr 19, 2011
  157. D. Das Sharma and A. Bhatt, “Transaction Layer Packet Compression”, US Patent No. 7,916,750, Issued Mar 29, 2011
  158. J. Ajanovic, M. Wagh, P. Sethi, D. Das Sharma, D. Harriman, et. al, “PCI-Express Enhancements and Extensions”, US Patent No. 7,899,943, Issued Mar 1, 2011
  159. D. Das Sharma and D. J. Harriman, “Link Interface Technique Including Data Indicator Symbols”, US Patent No. 7,899,111, Issued Mar 1, 2011
  160. D. Das Sharma, S. Neshvad, G. Rajamani, and H. Hoang, “Method and Apparatus for improving High-Availability in a PCI-Express link through predictive failure analysis”, US Patent No. 7,836,352, Issued Nov 16, 2010
  161. D. Das Sharma and A. Bhatt, “Using asymmetric lanes dynamically in a multi-lane serial link”, US Patent No. 7,809,969, Issued Oct 5, 2010
  162. D. Das Sharma, G. Rajamani, and H. Hoang, “Strategy to verify asynchronous links across chips”, US Patent No. 7,770,051, Issued Aug 3, 2010
  163. D. Das Sharma, “Link and lane level packetization scheme of encoding in serial links”, US Patent No. 7,769,048, Issued Aug 3, 2010
  164. D. Das Sharma and A. Bhatt, “Point-to-point link negotiation method and apparatus”, US Patent No. 7,757,020, Issued Jul 13, 2010
  165. D. Das Sharma, “Providing high availability in a PCI-ExpressTM link in the presence of lane faults”, US Patent No 7,730,376, Issued Jun 1, 2010
  166. D. Das Sharma, A. Bhatt, and D. Dunning, “A method and apparatus for meeting compliance for debugging and testing a multi-speed point-to-point link”, US Patent No. 7,633,877, Issued Dec 15, 2009
  167. R. Safranek and D. Das Sharma, “NoDMA Cache”, US Patent No. 7,571,294, Issued Aug 4, 2009
  168. D. Das Sharma, “Degradable network data path transmission scheme”, US Patent No. 7505486, Issued Mar 17, 2009
  169. D. Das Sharma, G. Rajamani, and H. Hoang, “Strategy to verify asynchronous links across chips”, US Patent No. 7464287, Issued Dec 9, 2008
  170. D. Das Sharma, “Providing high availability in a PCI-Express link in the presence of lane faults”, US Patent No. 7353443, Issued Apr 1, 2008
  171. R. Safranek and D. Das Sharma, “NoDMA Cache”, US Patent No. 7,296,127, Issued Nov 13, 2007
  172. M. Jen and D. Das Sharma, “Out-of-order servicing of read requests with minimal additional storage”, US Patent No. 7,228,362, Issued Jun 5, 2007
  173. D. Das Sharma, S. Muthrasanallur, and M. D. Smith, “Using information provided through tag space”, US Patent No. 7,120,722, Issued Oct 10, 2006
  174. J. Swanson and D. Das Sharma, “Method and apparatus for storing multiple entry types and ordering information in a single addressable storage array”,  US Patent No. 7,117,297, Issued Oct 3, 2006
  175. D. Das Sharma, A. Gupta, and W. Bryg, “System and method for memory migration in distributed memory multiprocessor systems”, US Patent No. 7,103,728, Issued Sep 5, 2006
  176. D. Das Sharma, “Method and apparatus for improving system performance through remote credit management”, US Patent No. 7,103,672, Issued Sep 5, 2006
  177. D. Das Sharma, “In-line wire error correction”, US Patent No. 7,096,414, Issued Aug 22, 2006
  178. D. Das Sharma, “Multiple ECC schemes to improve bandwidth”, US Patent No. 7,080,309, Issued Jul 18, 2006
  179. D. Das Sharma, “Multiple hardware partitions under one input/output hub”, US Patent No. 7,054,985, Issued May 30, 2006
  180. D. Das Sharma, “Directory-based cache coherency scheme for reducing memory bandwidth loss”, US Patent No. 7,051,166, Issued May 23, 2006
  181. D. Das Sharma and R. Rajamani, “CRC encoding scheme for conveying status information”, US Patent No. 7,047,475, Issued May 16, 2006
  182. D. Das Sharma, “Static end to end retransmit apparatus and method”, US Patent No. 6,938,091, Issued Aug 30, 2005
  183. D. Das Sharma, “Dynamic end to end retransmit apparatus and method”, US Patent No. 6,922,804, Issued Jul 26, 2005
  184. D. Das Sharma, “ECC code mechanism to detect wire stuck-at faults”, US Patent No. 6,910,169, Issued Jun 21, 2005
  185. D. Das Sharma and A. Gupta, “Virtualization of computer system interconnects”, US Patent No. 6832270, Issued Dec 14, 2004
  186. D. Das Sharma, D. A. Williamson, and E. M. Jacobs, “Method and apparatus for preventing underflow and overflow across an asynchronous channel”, US Patent No. 6,813,275, Issued Nov 2, 2004
  187. A. Gupta and D. Das Sharma, “System and method for input/output module virtualization and memory interleaving using cell map”, US Patent No. 6,807,603, Issued Oct 19, 2004
  188. D. Das Sharma, and E. S. Wolf,  “Method and apparatus for verifying error correcting codes”, US Patent No. 6,799,287, Issued Sep 28, 2004
  189. D. Das Sharma, “Multiple ECC schemes to improve bandwidth”, US Patent No. 6,675,344, Issued Jan 6, 2004
  190. D. Das Sharma, S. M. Ebner, J. A. Wickeraad, J. P. Cowan, and C. H. Jackson,  “Using Read current transactions for improved performance in directory-based coherent I/O systems”, US Patent No. 6,647,469, Issued Nov 11, 2003
  191. D. Das Sharma, S. M. Ebner, J. A. Wickeraad, J. P. Cowan, and C. H. Jackson,  “An apparatus and method for ensuring forward progress in coherent I/O systems”, US Patent No. 6,636,906, Issued Oct 21, 2003
  192. D. Das Sharma, E. M. Jacobs, and J. A. Wickeraad, “An apparatus and method for completing transactions in all flow-control classes”, US Patent No.  6,631,428, Issued Oct 7, 2003
  193. D. Das Sharma, “Apparatus and method using sub-cacheline transactions to improve system performance”, US Patent No. 6,629,213, Issued Sep 30, 2003
  194. K. Dickey and D. Das Sharma, “Method for assigning addresses to input/output devices”, US Patent No. 6,625,673, Issued Sep 23, 2003
  195. D. Das Sharma, “Credit initialization on systems with proactive flow-control”, US Patent No. 6,618,354, Issued Sep 9, 2003
  196. D. Das Sharma, A. Gupta, and D. Williamson, “Verification of asynchronous behavior”, US Patent No. 6,598,191, Issued Jul 22, 2003
  197. J. Swanson, D. Das Sharma, and J. Jones, “Reconfigurable FIFO interface to support multiple channels in bundled agent configurations”, US Patent No. 6,594,714, Issued Jul 15, 2003
  198. S. Ebner and D. Das Sharma, “Arbitration scheme for equitable distribution of bandwidth for agents with different bandwidth requirements”, US Patent No. 6,594,718, Issued Jul 15, 2003
  199. M. Lee, D. Das Sharma, and J. Bock, “Method and apparatus for evaluating a circuit”, US Patent No. 6,557,147, Issued Apr. 29, 2003
  200. D. Das Sharma, “ECC Code mechanism to detect wire stuck-at faults”, US Patent No. 6,473,877, Issued Oct 19, 2002
  201. D. Das Sharma, K. Hauck, and D. Li, “Verification of cache prefetch mechanism”, US Patent No. 6,412,046, Issued Jun 25, 2002
  202. D. Das Sharma, “Using page registers for efficient communication”, US Patent No. 6,285,686, Issued Sep 4, 2001
  203. D. Das Sharma, “System and method for efficient communication between buses”, US Patent No. 6,076,130, Issued Jun 13, 2000
  204. D. Das Sharma, “Formal verification of queue flow-control through model-checking”, US Patent No. 5,978,574, Issued Nov. 2, 1999
  205. D. Das Sharma and J. Wickeraad, “Method and apparatus for using the unused bits of a data packet to transmit additional information”, US Patent No. 5,944,843, Issued Aug 31, 1999