Journal Papers

  1. D. Das Sharma and N. S. Kim, “Special Issue on Interconnects for Chiplet Integration Technologies”, Editorial as Guest Editors, IEEE Micro, Jan-Feb 2025. (DOI: 10.1109/MM.2025.3534457)

  2. D. Das Sharma and R. Mahajan, “'Advanced packaging of chiplets for future computing needs’’, invited comment article, Nature Electronics, July 2024 (DOI: 10.1038/s41928-024-01175-3) https://www.nature.com/articles/s41928-024-01175-3. The editorial “Build it up” comments on this article “We begin with an article from researchers at Intel Corporation. … (It is a vision that has also provided the inspiration for this month’s cover image.)”

  3. D. Das Sharma, R. Blankenship, and D. Berger, “An Introduction to the Compute Express Link (CXL) Interconnect”, ACM Computing Surveys, Vol. 56, Issue 11, July 2024, https://dl.acm.org/doi/10.1145/3669900

  4. D. Das Sharma, “PCI-Express: Evolution of a Ubiquitous Load-Store Interconnect Over Two Decades and the Path Forward for the Next Two Decades”, IEEE Circuits and Systems Magazine, Q2, 2024, Vol 24, No. 2, DOI: 10.1109/MCAS.2024.3373556 on 2024-05-15.

  5. D. Das Sharma and S. Choudhary, “Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0”, IEEE Micro, Mar-Apr 2024, pp. 50-59 (Selected from IEEE Hot Interconnects)

  6. D. Das Sharma et. al, “High-performance, power-efficient three-dimensional System-in-Package designs with Universal Chiplet Interconnect Express”, Nature Electronics, Feb. 2024 (https://www.nature.com/articles/s41928-024-01126-y) (DOI: 10.1038/s41928-024-01126-y). Blog appears in Nature Electronics site. This research paper delves into the architectural and circuit aspects of the interconnect for 3D chiplets to deliver better power-efficient performance with a path for industry standardization.   Editorial on March, 2024 “feature(s)” this paper (https://www.nature.com/articles/s41928-024-01149-5)
  7. D. Das Sharma and T. Coughlin, “Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications”, IEEE Computer, Jan 2024
  8. D. Das Sharma, “Compute Express Link TM (CXLTM): Enabling heterogeneous
    data-centric computing with heterogeneous memory hierarchy    ”, IEEE Micro Mar-Apr 2023
  9. D. Das Sharma, “Universal Chiplet Interconnect Express (UCIe)®: An Open Industry Standard for Innovations with Chiplets at Package Level”, IEEE Micro Special Issue, Mar-Apr 2023
  10. D. Das Sharma, “Novel Composable and Scale-out Architectures using Compute Express LinkTM”, IEEE Micro Special Issue, Mar-Apr 2023
  11. D. Das Sharma et. al., “Universal Chiplet Interconnect Express (UCIe)®: An Open Industry Standard for Innovations with Chiplets at Package Level”, invited paper, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Oct 2022
  12. D. Das Sharma, "A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s with PAM-4 Signaling", IEEE Micro, Mar/ Apr 2022
  13. D. Das Sharma, "PCI Express 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling", IEEE Micro, Jan/ Feb 2021
  14. D. Das Sharma and D. K. Pradhan, “Job Scheduling in Mesh Multicomputers”, IEEE Transactions on Parallel and Distributed Systems, Vol. 9, No. 1, Jan 1998.
  15. D. Das Sharma and D. K. Pradhan, “Submesh Allocation in Mesh Multicomputers Using Busy-List: A Best-Fit Approach with Complete Recognition Capability”, Journal of Parallel and Distributed Computing, Vol. 36, No. 2, Aug 1996.
  16. D. Das Sharma and D. K. Pradhan, “Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategy for Cubic and Noncubic Allocation”, IEEE Transactions on Parallel and Distributed Systems, Vol. 6, No. 10, Oct. 1995.
  17. D. Das Sharma, F. J. Meyer, and D. K. Pradhan, “Yield Optimization of Modular and Redundant Multimegabit RAM’s: A Study of Effectiveness of Coding Versus Static Redundancy Using the Center-Satellite Model”, IEEE Transactions on VLSI Systems, Vol. 1, No. 4, Dec 1993.

Book Chapters

  1. Das Sharma and D. K. Pradhan, “An Efficient Coordinated Checkpointing Scheme for Multicomputers”, in Fault Tolerant Parallel and Distributed Systems, published by the IEEE Computer Society Press, 1996.
  2. D. K. Pradhan, D. Das Sharma, and N. H. Vaidya, “Roll-Forward Checkpointing Schemes”, in Lecture Notes in Computer Science, Hardware and Software Architectures for Fault Tolerance, Experiences and Perspcetives, published by Springer-Verlag, 1993.

Conference Papers/ Presentations

  1. D. Das Sharma, “Intel® 5520 Chipset: An I/O Hub Chipset for Server, Workstation, and High End Desktop”, Hot Chips 2009.
  2. D. Das Sharma et. al., “TwinCastle: A Multi-processor North Bridge Server Chipset”, Hot Chips 2005.
  3. G. Rajamani, H. Hoang, and D. Das Sharma, “A Low Overhead Method To Verify Components With Asynchronous Links”, DTTC, H1 05
  4. D. Das Sharma and G. Rajamani, “A configurable CRC implementation for supporting multiple link configurations”,  DTTC, 2H’03.
  5. A. Camilleri, D. Das Sharma, B. Odineal, and M. Heap, Presented a tutorial on techniques in using SMV-based model checking tool to formally verify designs at the 1995 HP Design and Test Technology Conference. 
  6. D. Das Sharma, “Processor Allocation in Hypercube Multicomputers: The Random Allocation Strategy”, 1995 ISCA International Conference on Parallel and Disributed Systems.
  7. D. Das Sharma, G. D. Holland, and D. K. Pradhan, “Subcube Level Time-Sharing in Hypercube Multicomputers”, 1994 International Conference on Parallel Processing.
  8. D. Das Sharma and D. K. Pradhan, “Job Scheduling in Mesh Multicomputers”, 1994 International Conference on Parallel Processing.
  9. D. Das Sharma and D. K. Pradhan, “Fast and Efficient Strategies for Cubic and Non-cubic Allocation in Hypercube Multiprocessors”, 1993 International Conference on Parallel Processing.
  10. D. Das Sharma and D. K. Pradhan, “A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers”, 1993 IEEE Symposium on Parallel and Distributed Processing.
  11. D. Das Sharma and D. K. Pradhan, “A Novel Approach for Subcube Allocation in Hypercube Multiprocessors”, 1992 IEEE Symposium on Parallel and Distributed Processing.
  12. D. Das Sharma, F. J. Meyer, and D. K. Pradhan, “Yield Optimization of Redundant Multimegabit RAM’s using the Center-Satellite Model”, 1992 IEEE International Conference on Wafer Scale Integration.