Personal:
I was born and raised in Odisha, India. My father is a retired college Professor and mother a housewife. I received my B.Tech. (Hons) in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur in 1989 and Ph.D. in Computer Systems Engineering from the University of Massachusetts, Amherst, in 1994. I live in Saratoga, California with my wife and our two sons. I enjoy reading, volunteering, and working on the preservation of the Jagannath culture and traditions in the Bay Area.
Professional:
I am an Intel Senior Fellow and co-GM of Memory and I/O Technologies at Intel Corporation, Santa Clara, California. I am also an elected board member of PCI-SIG since 2015 and have been serving as its treasurer since 2019. I am also the elected co-chair of CXL Board Technical Task Force and the elected chair of the UCIe Board.
My team is responsible for delivering industry-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCI Express®), Compute Express Link (CXL®), and Universal Chiplet Interconnect Express (UCIe TM ). We also deliver Intel’s proprietary Coherency Interconnect (QPI and UPI). We lead the pathfinding, architectural specification, design, and external ecosystem enabling all of these I/O technologies.
I joined the server design team at Hewlett-Packard Company in 1994 after completing my PhD. I led HP’s transition to PCI based I/O from its proprietary I/O bus as well as the transition to link-based coherent interfaces from bus-based systems in the Superdome servers. Our team joined Intel Corporation in 2001, as part of an acquisition. Ever since then I have been working on developing I/O technologies as well as their implementation in Intel’s CPUs and chipsets.
Involvement in Industry Standards Bodies
I am passionate about building composable systems using multi-generational and open industry standard interconnects. I believe that the industry does well when we all rally behind a common standard that evolves in a backwards compatible manner for decades. Open industry standards such as PCI-Express have fueled the virtuous cycle of compute which has proven to be win-win for all the entire ecosystem. Together, we increase the total available market through innovations that everyone, including our customers benefit. I have been fortunate enough to work for Intel Corporation which strongly believes in driving open industry standards and contributes significantly for the greater good, reflecting its vision of connecting and enriching every life in this planet.
I have been involved in the development of PCI Express (PCIe) since its inception in 2003 through seven generations of the technology evolution. Plug-and-play ensures that you can buy any company’s product (e.g., Graphics card, networking card, SSD, etc.) and it will work on a PCI-Express slot in a system. Backwards compatibility ensures that these devices will work if you upgrade the platform, or a new card will work in an old platform. PCI Express has emerged as the ubiquitous I/O interconnect in the industry, spanning the entire compute continuum from smart phones, laptops, PCs, servers, cloud, edge, 5G/6G, automotive, IoT devices, to supercomputers. In fact, it has moved from the “periphery” to be the central interconnect in modern computer systems with coherency and memory protocols running over it. PCI- Express has been an amazing journey. We double the data rate every generation within a fixed power, cost, and latency profile. We have seen compute infrastructure change significantly over the past two decades (e.g., smart phone, enterprise computing, cloud computing, IoT, 5G/6G, AI etc) and PCI-Express has evolved to meet the needs of each evolution, beyond the initial PC market it was supposed to serve. On the occasion of the 30-year anniversary of PCI-SIG in 2022, the industry consortium of ~1000 companies, that is responsible for developing PCI-Express technology, I did a public webinar (“The History of PCI IO Technology: 30 Years of PCI-SIG® Innovation”) summarizing this journey on behalf of PCI-SIG. I have done several talks, papers, articles, blogs, and webinars of various aspects of PCI-Express that can be found under Publications.
Compute Express Link (CXL) is the second industry standard I am proud of. We developed the technology inside Intel (known as Intel Accelerator Link) and donated the initial specification CXL 1.0 to launch the CXL consortium in 2019. Our goal was to drive an open ecosystem, like PCI-Express. We made the strategic choice of simplified coherency and memory semantics on top of PCI-Express infrastructure. This has resulted in a large ecosystem due to ease of deployment. Today CXL consortium boasts of 250+ member company world-wide and has generated two more generations of technology evolution in a fully backwards compatible manner. CXL enables heterogeneous computing for solving AI/ML problems effectively, provides memory bandwidth and capacity expansion to overcome the memory wall problem, and enables dynamically composable scale-up systems at a rack/ pod level. When we started CXL consortium, the industry in this space was fragmented with competing standards. Today the entire industry is aligned behind CXL and the competing standards have donated their assets (including IP) to CXL consortium. The industry is mature enough to do the right thing in the long run even though it may cause disruptions in the short run. CXL is the proof of the goodness of the entire ecosystem. Technical details of CXL can be found in this tutorial posted in arxiv. I have talked about my vision with CXL in various talks and papers, including this opening keynote at 2021 Hot Interconnects.
My latest industry effort is to enable chiplet innovation with an on-package interconnect UCIe. UCIe delivers the best-in-class power and performance. We developed the technology inside Intel, created a the consortium in March 2022 and donated the initial UCIe 1.0 specification to start the consortium. Today, UCIe has 125+ member companies including leaders in semiconductors, foundries, OSATs, IP houses, cloud provides etc. UCIe will foster innovations at the package level with chiplets the way PCI- Express and USB have triggered innovations at the board level. With UCIe retimer-enabled co-packaged optics, the industry can develop the composable systems with CXL protocol at the rack and pod level. UCIe will be instrumental in silicon and system development for decades. Details of UCIe can be found in webinars, whitepapers, papers, and invited talks listed here. I talked about my vision of how UCIe should evolve to include 3D chiplets in the opening keynote of 2023 International Test Conference. I strongly believe that with the strong industry participation that we have, we will unleash innovations to take computing to the next level with UCIe over the next few decades.