Dr. Debendra Das Sharma, PhD

Areas of expertise: Interconnect technologies (PCI Express, CXL, Coherency, On-package),CPU/ chipset architecture, I/O standards, design, and validation.

Technology Leadership

  • Delivered significant technical innovations to make PCIe the ubiquitous IO across the compute continuum since its inception in 2003, through seven generations of backwards compatible evolution to-date, despite significant industry transitions including hand-held, cloud, edge, 5G and AI.
  • Demonstrated ability to influence and lead the industry in inventing, launching, developing, and sustaining standards in IO technologies such as CXL with wide industry adoption. Able to rally the industry under CXL which was fragmented across multiple competing standards (CCIX, Open-CAPI, GenZ) with multiple generations of products.
  • Leading open chiplet ecosystem with the recent launch of Universal Chiplet Interconnect express (UCIe) in March 2022.
  • Prolific inventor – 180+ US patents and 450+ patents world-wide.
  • Trusted advisor to industry in IO – holding significant leadership positions in PCI-SIG (Board
  • of Directors), CXL (Co-chair of Board technical taskforce), and UCIe (Chair of UCIe).
  • Excels at effective communication of new technology benefits, with over 100 keynotes/ plenary talks/ distinguished lectures/ invite talks/ panels in leading technical conferences.
  • Editor of IEEE Micro and 2023 Award Committee member for IEEE CAS IPA.

Professional Experience

Sept 2001 – Present: Intel Corporation, Santa Clara, CA
Intel Senior Fellow and co-GM Memory and I/O Technologies (Dec 2021 – present)
Intel Fellow and Director, IO Technologies and Standards (Jan 2018 – Dec 2021)
Senior Principal Engineer and Director, IO Technologies and Standards (Apr 2010 – Jan 2018)
Principal Engineer (04/2004 – 04/2010), Tech. Lead (09/2001-04/2004), Digital Enterprise Group.

(Intel Senior Fellow is the highest level in technical ladder with ~25 Senior Fellows among 125000+ employees)

  • Extensive track record in delivering IO innovations to Intel and industry standards
    • Developed novel solution for PAM4 implementation at 64Gb/s per lane without jeopardizing latency or bandwidth for PCIe 6.0, CXL 3.0, as well as Intel’s cache coherent link (UPI)
    • Proposed and leading the optical extensions for PCI-Express
    • Co-invented CXL to deliver power-efficient performance in servers by overlaying coherency and memory semantics on PCI Express to drive optimal performance with accelerators and memory expansion drives.
    • Co-invented the die-to-die standard (UCIe) to deliver power-efficient performance in servers by overlaying coherency and memory semantics on an optimized die-to-die PHY for an open chiplet ecosystem and founded the UCIe consortium
    • Defining IP interfaces across the industry for plug-and-play IPs and standard validation collaterals (BFMs) which are accepted standards in the industry: PIPE for PHY to logic level interface in PCIe/ CXL, USB, SATA, Display Port, and UPI; LPIF for link layer to logical PHY in CXL; CPI for CXL.cache/memory to application layer; and SFI for PCIe/ CXL.io
    • Led the coherency interconnect (QPI, UPI) for Intel Xeon spanning two decades starting with the first move away from the front-side bus-based architecture
    • Led the MCP interconnect used for die-disaggregation for server CPUs with industry leading benchmarks in terms of area, power, bandwidth per shoreline, and latency.
  • Trusted industry leader in IO standards: PCI-Express, CXL, and UCIe.
    • Two decades of PCIe capability spanning pathfinding through compliance and interoperability enabling hundreds of products across the industry.
    • Influenced a fragmented compute industry to consolidate around CXL vs. many competing IO technologies (CCIX, OpenCAPI, NVLink), each with a deep product pipeline
    • Influenced a fragmented industry to consolidate around UCIe vs. many competing IO technologies (BoW, AIB, OpenHBI), each with a deep product pipeline by launching a consortium with key members from each of standards as promoters
    • Chair of UCIe Consortium
    • Co-chair of CXL Board Technical Task Force responsible for innovating and evolving CXL. Established the CXL consortium which has grown to 180+ member companies.
    • Director and Treasurer of PCI-SIG Board and chair of PHY Logical in PCI-SIG. Led PCI-Express through PCI-SIG, a consortium of 900+ member companies, with leading Intel products since its inception through six generations and two decades.
  • Lead I/O Architect at Intel responsible for I/O in Intel products
    • Leads a team of >25 experienced engineers, architects and technologists across different states and countries, responsible for a wide portfolio of IO technologies, driving technologies internally and externally through industry standards.
    • Intel-wide charter covers strategy, architecture, standardization, validation, and ecosystem enabling.
    • Lead I/O architect for server CPUs spanning PCIe, CXL, cache coherency (UPI), and MCP interconnects for die-disaggregation responsible for technology readiness, architecture, micro-architecture with industry-leading performance, power, and area metrics, and overseeing implementation from pre-silicon to post-silicon through product launch for more than a decade
    • Lead chipset designer for server chipsets leading PCIe and UPI transitions within Intel and subsequently led the migration of PCIe to CPU during PCIe Gen 3.

Sept 1994 – Sept 2001: Hewlett-Packard Corporation, Cupertino, CA

  • Lead I/O Architect for Superdome servers defining and delivering HP’s I/O strategy by migrating to PCI from its proprietary interconnect through a cache-coherent I/O hub

Patents and publications

  • 180+ US Patents and 450+ world-wide patents covering foundational aspects of I/O technologies such as PCIe, CXL, UPI, UCIe, MCP Links (e.g., PCIe encoding, PCIe Protocol, CXL protocol, UPI Protocol and encoding, PAM4 with low-latency correction, etc.)
  • 100+ keynotes, plenary talk, distinguished lectures, talks and panels in IEEE Hot-chips, IEEE Hot Interconnects, IEEE 3DIC, IEEE Coolchips, Supercomputing, PCI-SIG Developers Conference, CXL Consortium Technical Event, Intel Developer Forum, Flash Memory Summit, SNIA Storage Developers Conference, Open Server Summit, Open Fabrics Alliance, Carnegie-Mellon University, Texas A&M University, Georgia Tech, UC Irvine, and Univ of Illinois, Urbana-Champaign. Sought by media for technology deep-dive in various articles and interviews.

Education

  • Ph.D. in Computer Engineering, Univ of Massachusetts, Amherst. 1994 Areas of research: Parallel architectures, VLSI, Fault-tolerance
  • B.Tech. (Hons.) in Computer Science and Engineering,Indian Institute of Technology, Kharagpur, India. 1989. (9.25/10)

Awards

  • 2024 Edward J. McCluskey Technical Achievement Award by IEEE Computer Society, “For architectural innovations driving open composable systems at package, node, Rack, and Pod levels with PCI-Express, CXL, and UCIe standards”. 
  • 2022 Industrial Pioneer Award by IEEE Circuits and Systems Society, “For pioneering innovations and industry leadership in establishing PCI-Express and Computer Express Link as the ubiquitous I/O interconnect standards”. 
  • Lifetime Contribution Award by PCI-SIG in 2022. Established in 2022 on the occasion of the 30th anniversary of PCI-SIG
  • 2021 IEEE Region 6 Outstanding Engineer Award “For pioneering innovations and industry leadership in IEEE technical fields and establishing PCI-Express and Compute Express Link I/O interconnects”.
  • Distinguished Alumnus Award, IIT, Kharagpur, September 2019
  • Intel Top Innovator Award, 2022.
  • Intel Achievement Award, Intel, 2008.“For Tylersburg – the first chipset that covers 5 discrete product segments with one design.”
  • PCI-Express Achievement in Excellence Award, PCI-SIG, 2005. “In recognition of your contributions to the PCI Express* Electrical Workgroup in establishing the next generation of Data Rates for PCI Express 2.0.”